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ICs for Communications
Digital Answering Machine with Full Duplex Speakerphone SAM EC PSB 4860 Version 2.1
Data Sheet 10.97
DS 1
PSB 4860 Revision History: Previous Version: Page Page (in previous (in new Version) Version)
Current Version: 10.97 Preliminary Data Sheet 09.97 Subjects (major changes since last revision)
Index added
Edition 10.97 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, HL TS (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PSB 4860
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.1.14 2.1.15 2.1.16 2.1.17 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Analog Featurephone with Digital Answering Machine . . . . . . . . . . . . . . .19 Featurephone with Digital Answering Machine for ISDN Terminal . . . . . .21 DECT Basestation with Integrated Digital Answering Machine . . . . . . . . .22 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Full Duplex Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Echo Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Line Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 CNG Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Alert Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 CPT Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Caller ID Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Speech Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 File Definition and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 User Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 High Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . .67 Low Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . . .75 Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Special Notes on File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Reset and Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3 10.97
Semiconductor Group
PSB 4860
Table of Contents 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 3 3.1 3.2 3.3 3.3.1 3.3.2 4 4.1 4.2 4.3 5
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Page
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Clock Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 SSDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Auxiliary Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Hardware Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. DigiTapeTM, MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG.
Semiconductor Group
4
10.97
PSB 4860
List of Figures General Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6:
Page 13 18 19 20 21 22
Pin Configuration of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of PSB 4860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Full Duplex Speakerphone with Digital Answering Machine . . . . Featurephone with Answering Machine for ISDN Terminal . . . . . . . . . . . DECT Basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Units Figure 7: Functional Units - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8: Functional Units - Recording a Phone Conversation . . . . . . . . . . . . . . . . Figure 9: Functional Units - Simultaneous Internal and External Call . . . . . . . . . . . Figure 10: Speakerphone - Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11: Speakerphone - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12: Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13: Echo Cancellation Unit - Typical Room Impulse Response . . . . . . . . . . . Figure 14: Echo Suppression Unit - States of Operation. . . . . . . . . . . . . . . . . . . . . . Figure 15: Echo Suppression Unit - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . Figure 16: Speech Detector - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17: Speech Comparator - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18: Speech Comparator - Interdependence of Parameters . . . . . . . . . . . . . . Figure 19: Echo Suppression Unit - Automatic Gain Control. . . . . . . . . . . . . . . . . . . Figure 20: Line Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . Figure 21: DTMF Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22: CNG Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23: Alert Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24: CPT Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25: CPT Detector - Cooked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26: Caller ID Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27: DTMF Generator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28: Speech Coder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29: Speech Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 30: Analog Front End Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . Figure 31: Digital Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 32: Universal Attenuator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 33: Automatic Gain Control Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . Figure 34: Equalizer - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management Figure 35: Memory Management - Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36: Memory Management - Directory Structure . . . . . . . . . . . . . . . . . . . . . . . Figure 37: Audio File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Semiconductor Group 5
23 25 26 27 27 28 29 30 31 32 35 36 39 42 44 45 46 47 47 49 51 52 54 55 56 58 59 61
63 63 64 64
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PSB 4860
List of Figures
Page
Figure 39: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Miscellaneous Figure 40: Operation Modes - State Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interfaces Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68:
IOM(R)-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 IOM(R)-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 IOM(R)-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 IOM(R)-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SSDI Interface - Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SSDI Interface - Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . 92 Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . . 93 Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . . 93 Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Configuration Register Write Access or Register Read Command . . . . . 96 ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . 99 ARAM/DRAM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . 100 ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 101 ARAM/DRAM Interface - Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . 101 EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 102 EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 102 Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 103 Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . 104 Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . 105 Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . 105 Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 108
Electrical Characteristics Figure 69: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Timing Diagrams Figure 70: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 71: SSDI/IOM(R)-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . Figure 72: SSDI/IOM(R)-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . Figure 73: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Semiconductor Group 6
231 232 232 234
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List of Figures Figure 74: Figure 75: Figure 76: Figure 77: Figure 78: Figure 79: Figure 80: Figure 81: Figure 82: Figure 83: Figure 84: Figure 85:
Page 235 236 237 238 239 240 241 242 243 244 245 246
Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Front End Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . Memory Interface - Samsung Data Write . . . . . . . . . . . . . . . . . . . . . . . . Memory Interface - Samsung Data Read . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Semiconductor Group
7
10.97
PSB 4860
List of Tables General Table 1:
Page
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Units Table 2: Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 3: Echo Cancellation Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 4: Speech Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 5: Speech Comparator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 6: Attenuation Control Unit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 7: SPS Output Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 8: Automatic Gain Control Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 9: Fixed Gain Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 10: Speakerphone Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 11: Line Echo Cancellation Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 12: DTMF Detector Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 13: DTMF Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 14: DTMF Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 15: CNG Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 16: CNG Detector Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 17: Alert Tone Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 18: Alert Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 19: CPT Detector Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 20: CPT Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 21: Caller ID Decoder Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 22: Caller ID Decoder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 23: Caller ID Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 24: DTMF Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 25: Speech Coder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 26: Speech Coder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 27: Speech Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 28: Analog Front End Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 29: Digital Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 30: Universal Attenuator Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 31: Automatic Gain Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 32: Equalizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Memory Management - General Table 33: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 34: Memory Management Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 35: Memory Management Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Memory Management - Commands Table 36: Initialize Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Semiconductor Group 8 10.97
PSB 4860
Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60:
Initialize Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Activate Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Activate Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Activate Memory Result Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Open File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Open Next Free File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Open Next Free File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Seek Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Cut File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Compress File Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Memory Status Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Memory Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Garbage Collection Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Access File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Access File Descriptor Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Read Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Write Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Set Address Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DMA Read Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DMA Read Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 DMA Write Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Block Erase Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Execution Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Miscellaneous Table 61: Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 62: SPS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 63: Power Down Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 64: Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 65: Hardware Configuration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 66: Frame Synchronization Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 67: Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Table 68: File Command Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Table 69: Module Weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Interfaces Table 70: Table 71: Table 72: Table 73: Table 74: Table 75:
SSDI vs. IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 IOM(R)-2 Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 SSDI Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Control of ALS Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Analog Front End Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Analog Front End Interface Clock Cycles. . . . . . . . . . . . . . . . . . . . . . . . . .93
9 10.97
Semiconductor Group
PSB 4860
Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: Table 86:
Command Words for Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Address Field W for Configuration Register Write . . . . . . . . . . . . . . . . . . .97 Address Field R for Configuration Register Read . . . . . . . . . . . . . . . . . . .97 Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Address Line Usage (ARAM/DRAM Mode) . . . . . . . . . . . . . . . . . . . . . . .100 Refresh Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Address Line Usage (Samsung Mode). . . . . . . . . . . . . . . . . . . . . . . . . . .103 Flash Memory Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Static Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Multiplex Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Electrical Characteristics Table 87: Status Register Update Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Semiconductor Group
10
10.97
PSB 4860
Overview 1
General General
Overview
Combined with an analog front end the PSB 4860 provides a solution for embedded or stand alone answering machine applications. Together with a standard microcontroller for analog telephones these two chips form the core of a featurephone with full duplex speakerphone and answering machine capabilities. The chip features recording by DigiTapeTM, a family of high performance algorithms. Messages recorded with DigiTapeTM can be played back with variable speed without pitch alteration. Messages recorded with a higher bitrate can be converted into messages with a lower bitrate arbitrarily. Current members of DigiTape (TM) span the range from 3.3 kbit/s to 10.3 kbit/s. Furthermore the PSB 4860, V2.1 has a full duplex speakerphone, a caller ID decoder, DTMF recognition and generation and call progress tone detection. The frequency response of cheap microphones or loudspeakers can be corrected by a programmable equalizer. Messages and user data can be stored in ARAM/DRAM or flash memory which can be directly connected to the PSB 4860. The PSB 4860 also supports a voice prompt EPROM for fixed announcements. The PSB 4860 provides an IOM(R)-2 compatible interface with two channels for speech data. Alternatively to the IOM(R)-2 compatible interface the PSB 4860 supports a simple serial data interface (SSDI) with separate strobe signals for each direction (linear PCM data, one channel). A separate interface is used for a glueless connection to the PSB 4851. The chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. For data retention the PSB 4860 supports a power down mode where only the real time clock and the memory refresh (in case of ARAM/DRAM) are operational. The PSB 4860 supports interface pins to +5 V levels.
Semiconductor Group
11
10.97
Digital Answering Machine with Full Duplex Speakerphone SAM EC
PSB 4860
Version 2.1
CMOS
1.1
Features
Digital Functions * * * * * * * * * * * * * * * * High performance recording by DigiTapeTM Selectable compression rate (3.3 kbit/s, 10.3 kbit/s) Variable playback speed Support for ARAM or Flash Memory Optional voice prompt EPROM Full duplex speakerphone DTMF generation and detection Call progress tone detection Caller ID recognition Direct memory access Real time clock Equalizer Automatic gain control Automatic timestamp Auxiliary parallel port Ultra low power refresh mode
P-MQFP-80
General Features * SSDI/IOM(R)-2 compatible interface * Serial control interface for programming
Type PSB 4860
Semiconductor Group
Package P-MQFP-80
12 10.97
PSB 4860
Overview 1.2 Pin Configuration (top view)
60 VDD MA4 MA5 MA6 MA7 VSS VDD MA8 MA9 MA10 MA11 VSS VDD MA12 MA13 MA14 MA15 VSS RST VDDP 61
VSS VSS VDD VSS RO MA3 MA2 MA1 MA0 MD7 MD6 VDD VSS MD5 MD4 MD3 MD2 MD1 MD0 VDDP 50 41 40 VSS VDD SPS1 SPS0 CAS1/FCS CAS0/ALE RAS/FOE VPRD/FCLE W/FWE FRDY VSS VDD DRST DXST DD/DR DU/DX DCL FSC VSS VDD 70
SAM EC PSB 4860
30
80 1 10 20
21
Figure 1
Pin Configuration of PSB 4860
Semiconductor Group
VDDA XTAL1 XTAL2 VSSA OSC1 OSC2 VDD CLK VSS INT SCLK SDX SDR CS VDD VSS AFEFS AFECLK AFEDD AFEDU
13
10.97
PSB 4860
Overview 1.3 Table 1 Pin No.
P-MQFP-80
Pin Definitions and Functions Pin Definitions and Functions Symbol Dir. Reset Function Power supply (5V 10 %) Power supply for the interface. Power supply (3.0 V - 3.6 V) Power supply for logic.
41, 80
VDDP
7, 15, 21, VDD 29, 39, 49, 58, 61, 67, 73 1 4
VDDA VSSA
-
-
Power supply (3.0 V - 3.6 V) Power supply for clock generator. Power supply (0 V) Ground for clock generator. Power supply (0 V) Ground for logic and interface.
9, 16, 22, VSS 30, 40, 48, 57, 59, 60, 78, 66, 72 17 AFEFS
O
L
Analog Frontend Frame Sync: 8 kHz frame synchronization signal for the analog front end. Analog Frontend Clock: Clock signal for the analog front end. Analog Frontend Data Downstream: Data output to the analog frontend. Analog Frontend Data Upstream: Data input from the analog frontend. Reset: Active high reset signal. Data Frame Synchronization: 8 kHz frame synchronization signal (IOM(R)-2 and SSDI mode). Data Clock: Data Clock of the serial data interface.
18 19 20 79 23
AFECLK O AFEDD AFEDU RST FSC O I I I
L L -
24
DCL
I
-
Semiconductor Group
14
10.97
PSB 4860
Overview Table 1 26 Pin Definitions and Functions DD/DR I/OD I 25 DU/DX I/OD O/ OD 27 28 14 11 13 12 10 DXST DRST CS SCLK SDR SDX INT O I I I I O/ OD O/ OD L H H IOM(R)-2 Compatible Mode: Receive data from IOM(R)-2 controlling device. SSDI Mode: Receive data of the strobed serial data interface. IOM(R)-2 Compatible Mode: Transmit data to IOM(R)-2 controlling device. SSDI Mode: Transmit data of the strobed serial data interface. DX Strobe: Strobe for DX in SSDI interface mode. DR Strobe: Strobe for DR in SSDI interface mode. Chip Select: Select signal of the serial control interface (SCI). Serial Clock: Clock signal of the serial control interface (SCI). Serial Data Receive: Data input of the serial control interface (SCI). Serial Data Transmit: Data Output of the serial control interface (SCI). Interrupt New status available.
Semiconductor Group
15
10.97
PSB 4860
Overview Table 1 52 53 54 55 62 63 64 65 68 69 70 71 74 75 76 77 42 43 44 45 46 47 50 51 35 Pin Definitions and Functions MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 CAS0/ ALE CAS1/ FCS RAS/ FOE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O L1) L L L L L L L L L L L L L L L H2) Memory Address 0-15: Multiplexed address outputs for ARAM, DRAM access. Non-multiplexed address outputs for voice prompt EPROM. Auxiliary Parallel Port: General purpose I/O.
Memory Data 0-7: Memory (ARAM, DRAM, Flash Memory, EPROM) data bus.
ARAM, DRAM: Column address strobe for memory bank 0 or 1. Flash Memory: Address Latch Enable for address lines A16-A23. Chip select signal for Flash Memory
36
O
34
O
H2)
ARAM, DRAM: Row address strobe for both memory banks. Flash Memory: Output enable signal for Flash Memory. ARAM, DRAM: Read signal for voice prompt EPROM. Flash Memory: Command latch enable for Flash Memory.
33
VPRD/ FCLE
O
H2)
Semiconductor Group
16
10.97
PSB 4860
Overview Table 1 32 Pin Definitions and Functions W/FWE O H2) ARAM, DRAM: Write signal for all memory banks. Flash Memory: Write signal for Flash Memory. Flash Memory Ready Input for Ready/Busy signal of Flash Memory Auxiliary Oscillator: Oscillator loop for 32.768 kHz crystal. Alternative AFECLK Source 13,824 MHz Oscillator: XTAL1: External clock or input of oscillator loop. XTAL2: output of oscillator loop for crystal. Multipurpose Outputs: General purpose, speakerphone, address lines or status Reserved Output Must be left open.
31 5 6 8 2 3 37 38 56
1) 2)
FRDY OSC1 OSC2 CLK XTAL1 XTAL2 SPS0 SPS1 RO
I I O I I O O O O
Z Z L L -
These lines are driven low with 125 A until the mode (address lines or auxiliary port) is defined. These lines are driven high with 70 A during reset.
Semiconductor Group
17
10.97
PSB 4860
Overview 1.4
1
Logic Symbol
RST AFECLK
CLK OSC1 OSC2
XTAL1 XTAL2 DU/DX DD/DR DCL FSC DXST
PSB 4851
AFEFS AFEDD AFEDU
IOM(R)-2 SSDI
PSB 4860
VDD VDDA VSS
DRST INT SDX SDR SCLK CS
SCI
CAS0/ CAS1/ FCS MA0-MA15 MD0-MD7 ALE
RAS/ FOE
W/ FWE
VPRD/ FCLE FRDY
Memory
Figure 2
Logic Symbol of PSB 4860
Semiconductor Group
18
10.97
PSB 4860
Overview 1.5 Functional Block Diagram
RST
OSC1 OSC2
XTAL1 XTAL2
Reset and Timing Unit Data Interface
DRST DXST DU/DX DD/DR DCL FSC
AFECLK AFEFS AFEDD AFEDU Analog Front End Interface
DSP
Control Interface
INT SDX SDR SCLK CS
Memory Interface
FRDY
MA0-MA15 MD0-MD7 CAS0/ CAS1/ ALE FCS
RAS/ FOE
W/ FWE
VPRD/ FCLE
Figure 3 1.6
Block Diagram of PSB 4860 System Integration
The PSB 4860 combined with an analog front end (PSB 4851) can be used in a variety of applications. This combination offers outstanding features like full duplex speakerphone and emergency operation. Some applications are given in the following sections. 1.6.1 Analog Featurephone with Digital Answering Machine
Figure 4 shows an example of an analog telephone system. The telephone can operate during power failure by line powering. In this case only the handset and ringer circuit are active. All other parts of the chipset are shut down leaving enough power for the external microcontroller to perform basic tasks like keyboard monitoring.
Semiconductor Group 19 10.97
PSB 4860
Overview For answering machine operation the voice data is stored in ARAM or Flash Memory devices. In addition, voice prompts can be played back from an optional voice prompt EPROM. If flash memory is used the functionality of the voice prompt EPROM can be realized by the flash memory devices. The microcontroller can use the memory attached to the PSB 4860/PSB 4851 to store and retrieve binary data.
ARAM Flash Memory
PSB 4860 PSB 4851
Voice Prompt EPROM
077-3445
tip/ ring
Microcontroller
line
Figure 4
Analog Full Duplex Speakerphone with Digital Answering Machine
Semiconductor Group
20
10.97
PSB 4860
Overview 1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal
Figure 5 shows an ISDN featurephone that takes full advantage of two simultaneous connections. In this application one channel of the PSB 4851 interfaces to the handset and speakerphone while the other provides an interface for an external analog device (e.g. FAX machine).
Flash Memory
PSB 4860 PSB 4851
IOM(R)-2 Power Controller PSB 2120/1 SCI SLIC
077-3445
Microcontroller
PSB 2186 ISAC(R)-S TE
S0-BUS
POTS
Figure 5
Featurephone with Answering Machine for ISDN Terminal
In addition, the two channels of the PSB 4851 can be used for holding two connections simultaneously. One connection can be switched to the handset and the other to the speakerphone box. Local three party conferences are also possible.
Semiconductor Group
21
10.97
PSB 4860
Overview 1.6.3 DECT Basestation with Integrated Digital Answering Machine
Figure 6 shows a DECT basestation based on the PSB 4860/PSB 4851 chipset. In this application it is possible to service both an external call and an internal call at the same time. For programming the serial control interface (SCI) is used while voice data is transferred via the strobed serial data interface (SSDI/IOM(R)-2).
Flash Memory
PSB 4860 PSB 4851
SSDI/IOM(R)-2
Antenna
SCI
077-3445
tip/ ring Microcontroller
Burstmode Controller
DECT HF
line
Figure 6
DECT Basestation
Semiconductor Group
22
10.97
PSB 4860
Functional Description 2
Functional Units Functional Units
Functional Description
The PSB 4860 contains several functional units that can be combined with almost no restrictions to perform a given task. Figure 7 gives an overview of the important functional units.
SSDI/IOM(R)-2 Channel 1 IOM(R)-2 Channel 2
S6
S8
loudspeaker microphone
S4
I1 I2 I3
S5
I1 I2 I3 I1 I2
S7 S11
I1 I2 I3
S13
S3 S9
S14
acoustic side
Speech Decoder Memory Speech Coder
Universal Attenuator
Speakerphone
line side
DTMF Generator
I1
S10 S2
I1 I1 I2 I3 I2
S12
I3 I4 I1 I2
I1
I2 I1
line out line in
Line Echo Canceller
AGC
Equalizer
S1 S15
I1 CNG Detector I1 Alert Tone Detector I1 CPT Detector
S16 S17
I1 CID Decoder
S18
I1 DTMF Detector SCI
signal summation: I1 I2 I3
signal sources: S1,...,S18
Figure 7
Functional Units - Overview
Semiconductor Group
23
10.97
PSB 4860
Functional Description Each unit has one or more signal inputs (denoted by I). Most units have at least one signal output (denoted by S). Any input I can be connected to any signal output S. In addition to the signals shown in figure 7 there is also the signal S0 (silence), which is useful at signal summation points. Table 2 lists the available signals within the PSB 4860 according to their reference points. Table 2 Signal S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 Signal Summary Description Silence Analog line input (channel 1 of PSB 4851 interface) Analog line output (channel 1 of PSB 4851 interface) Microphone input (channel 2 of PSB 4851 interface) Loudspeaker/Handset output (channel 2 of PSB 4851 interface) Serial interface input, channel 1 Serial interface output, channel 1 Serial interface input, channel 2 Serial interface output, channel 2 DTMF generator output DTMF generator auxiliary output Speakerphone output (acoustic side) Speakerphone output (line side) Speech decoder output Universal attenuator output Line echo canceller output Automatic gain control output (after gain stage) Automatic gain control output (before gain stage) Equalizer output
Semiconductor Group
24
10.97
PSB 4860
Functional Description The following figures show the connections for two typical states during operation. Units that are not needed are not shown. Inputs that are not needed are connected to S0 which provides silence (denoted by 0). In figure 8 a hands-free phone conversation is currently in progress. The speech coder is used to record the signals of both parties. The alert tone detector is used to detect an alerting tone of an off-hook caller id request while the CID decoder decodes the actual data transmitted in this case.
loudspeaker microphone
0 0 0 Speech coder
acoustic side
Memory
Speakerphone
line side
AGC 0 line out line in Line Echo Canceller CID decoder Alert Tone Detector SCI 0 0
Figure 8
Functional Units - Recording a Phone Conversation
Semiconductor Group
25
10.97
PSB 4860
Functional Description In figure 9 a phone conversation using the speakerphone is in progress. One party is using the base station of a DECT system while the other party is using a mobile handset. At the same time an external call is serviced by the answering machine. In the current state a message (recorded or outgoing) is being played back. In this case the DTMF detector is used to detect signals for remote access while the CPT detector is used to determine the end of the external call.
SSDI/IOM(R)-2 Channel 1
loudspeaker microphone
0 0
00
0
acoustic side
Equalizer
Speakerphone
line side
Speech decoder 0 line out line in Line Echo Canceller CPT decoder DTMF Detector SCI 0 0 Memory
Figure 9
Functional Units - Simultaneous Internal and External Call
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PSB 4860
Functional Description 2.1 Functional Units
In this section the functional units of the PSB 4860 are described in detail. The functional units can be individually enabled or disabled. 2.1.1 Full Duplex Speakerphone
The speakerphone unit (figure 10) is attached to four signals (microphone, loudspeaker, line out and line in). The two input signals (microphone, line in) are preceded by a signal summation point.
I1 I2
microphone
S11
loudspeaker
a c o u s t i c s i d e
line out l i n e s i d e
S12
Speakerphone
line in
I3 I4
Figure 10 Speakerphone - Signal Connections Internally, this unit can be divided into an echo cancellation unit and an echo suppression unit (figure 11). The echo cancellation unit provides the attenuation Gc while the echo suppression unit provides the attenuation Gs. The total attenuation ATT of the speakerphone is therefore ATT=GC+Gs.
microphone
loudspeaker
Echo Cancellation Gc
Echo Suppression GS
line out
line in
Figure 11 Speakerphone - Block Diagram The echo suppression unit can be enabled without the echo cancellation unit. If the echo cancellation unit is disabled, the echo suppression unit still provides speakerphone functionality, albeit only half duplex. As the echo cancellation must be disabled during recording or playback of speech data, this option allows for speakerphone operation
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PSB 4860
Functional Description even if recording or playback is going on. The echo suppression unit is also used to provide additional attenuation if the echo cancellation unit cannot provide all of the required attenuation itself. 2.1.2 Echo Cancellation
A simplified block diagram of the echo cancellation unit is shown in figure 12.
microphone
line out
-
Control
NLMS
FIR Filter
loudspeaker
line in
Figure 12 Echo Cancellation Unit - Block Diagram The echo cancellation unit consists of an finite impulse response filter (FIR) that models the expected acoustic echo, an NLMS based adaption unit and a control unit. The expected echo is subtracted from the actual input signal from the microphone. If the model is exact and the echo does not exceed the length of the filter then the echo can be completely cancelled. However, even if this ideal state can be achieved for one given moment the acoustic echo usually changes over time. Therefore the NLMS unit continuously adapts the coefficients of the FIR filter. This adaption process is steered by the control unit. As an example, the adaption is inhibited as long as double talk is detected by the control unit. Furthermore the control unit informs the echo suppression unit about the achieved echo return loss. Table 3 shows the registers associated with the echo cancellation unit. Table 3 Register SAELEN SAEATT SAEGS Echo Cancellation Unit Registers # of Bits 9 15 3 Name LEN ATT GS Comment Length of FIR filter Attenuation reduction during double-talk Global scale (all blocks)
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PSB 4860
Functional Description Table 3 SAEPS1 SAEPS2 Echo Cancellation Unit Registers 3 3 AS FB Partial scale (for blocks >= SAEPS2:FB) First block affected by partial scale
The length of the FIR filter can be varied from 127 to 511 taps (15.875ms to 63.875ms). The taps are grouped into blocks. Each block contains 64 taps. The performance of the FIR filter can be enhanced by prescaling some or call of the coefficients of the FIR filter. A coefficient is prescaled by multiplying it by a constant. The advantage of prescaling is an enhanced precision and consequently an enhanced echo cancellation. The disadvantage is a reduced echo cancellation performance if the signal exceeds the maximal coefficient value. More precisely, if a coefficient at tap Ti is scaled by a factor Ci then the level of the echo (room impulse response) must not exceed Max/ Ci (Max: Maximum PCM value). As an example figure shows a typical room impulse response. A
0.5
0.25
t0.25
t
Figure 13 Echo Cancellation Unit - Typical Room Impulse Response First of all, the echo never exceeds 0.5 of the maximum value. Furthermore the echo never exceeds 0.25 of the maximum value after time t0.25. Therefore all coefficients can be scaled by a factor of 2 and all coefficients for taps corresponding to times after t0.25 can be scaled a factor of 4. The echo cancellation unit provides three parameters for scaling coefficients. The first parameter (GS) determines a scale for all coefficients. The second parameter (FB) determines the first block for which an additional scale (PS) takes effect. This feature can be used for different default settings like large or small rooms.
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PSB 4860
Functional Description 2.1.3 Echo Suppression
The echo suppression unit can be in one of three states: * transmit state * receive state * idle state In transmit state the microphone signal drives the line output while the line input is attenuated. In receive state the loudspeaker signal is driven by the line input while the microphone signal is attenuated. In idle state both signal paths are active with evenly distributed attenuation.
idle state
microphone loudspeaker
line out line in
transmit state
microphone loudspeaker
line out line in
receive state
microphone loudspeaker
line out line in
Figure 14 Echo Suppression Unit - States of Operation
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PSB 4860
Functional Description Figure15 shows the signal flow graph of the echo suppression unit in more detail.
microphone
AGCX
GHX
LGAX
line out
SDX
SCAS
Attenuation Control
SCLS
SDR
loudspeaker
LGAR
GHR
AGCR
line in
Figure 15 Echo Suppression Unit - Signal Flow Graph State switching is controlled by the speech comparators (SCAS, SCLS) and the speech detectors (SDX, SDR). The amplifiers (AGCX, AGCR, LGAX, LGAR) are used to achieve proper signal levels for each state. All blocks are programmable. Thus the telephone set can be optimized and adjusted to the particular geometrical and acoustical environment. The following sections discuss each block of the echo suppression unit in detail.
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PSB 4860
Functional Description 2.1.3.1 Speech Detector
For each signal source a speech detector (SDX, SDR) is available. The speech detectors are identical but can be programmed individually. Figure 16 shows the signal flow graph of a speech detector.
OFF
LIM LP1 PD PDS PDN LP2
LP1 LIM
Signal Preprocessing
LP2S LP2N LP2L
Background Noise Monitor
Figure 16 Speech Detector - Signal Flow Graph The first three units (LIM, LP1, PD) are used for preprocessing the signal while the actual speech detection is performed by the background noise monitor. Background Noise Monitor The tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. Therefore the Background Noise Monitor consists of the Low-Pass Filter 2 (LP2) and the offset in two separate branches. Basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). In contrast, background noise can be regarded approximately stationary from its average power. Low-Pass Filter 2 provides different time constants for noise (non-detected speech) and speech. It determines the average of the noise reference level. In case of background noise the level at the output of LP2 is approximately the level of the input. As in the other branch an additional offset OFF is added to the signal, the comparator signals noise. At speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the LP2-branch. If the difference exceeds the offset OFF, the
Semiconductor Group
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PSB 4860
Functional Description comparator signals speech. Therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). A small fade constant (LP2N) enables fast settling of LP2 to the average noise level after the end of speech recognition. However, a too small time constant for LP2N can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. It is recommended to choose a large rising constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is not recommended to choose an infinite LP2S because then approaching the noise level is disabled. During continuous speech or tones the LP2 will be charged until the limitation LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This limitation permits transmission of continuous tones and "music on hold". The offset stage represents the estimated difference between the speech signal and averaged noise. Signal Preprocessing As described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. In very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. Therefore a peak detection is required in front of the Noise Monitor. The main task of the Peak Detector (PD) is to bridge the very short speech pauses during a monolog so that this time constant has to be long. Furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. But if no speech is recognized the noise low-pass LP2 must be charged faster to the average noise level. In addition, the noise edges are to be smoothed. Therefore two time constants are necessary. As the peak detector is very sensitive to spikes, the low-pass LP1 filters the incoming signal containing noise in a way that main spikes are eliminated. Due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. To compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. Hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. The limitation of the logarithmic amplifier can be programmed via the parameter LIM. LIM is related to the maximum PCM level. A signal exceeding the limitation defined by LIM is getting amplified logarithmically, while very smooth system noise below is neglected. It should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path. Table 6 shows the parameters for the speech detector.
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PSB 4860
Functional Description Table 4 LIM OFF PDS PDN LP1 LP2S LP2N LP2L Speech Detector Parameters Comment Limitation of log. amplifier Level offset up to detected noise Peak decrement PD1 (speech) Peak decrement PD1 (noise) Time constant LP1 Time constant LP2 (speech) Time constant LP2 (noise) Maximum value of LP2 1 1 1 1 1 1 1 1 0 to 95 dB 0 to 95 dB 1 to 2000 ms 1 to 2000 ms 1 to 2000 ms 2 to 250 s 1 to 2000 ms 0 to 95 dB
Parameter # of bytes Range
The input signal of the speech detector can be connected to either the input signal of the echo suppression unit (as shown for SDX) or the output of the associated AGC (as shown for SDR).
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PSB 4860
Functional Description 2.1.3.2 Speech Comparators (SC)
The echo suppression unit has two identical speech comparators (SCAS, SCLS). Each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. As SCAS and SCLS are identical, the following description holds for both SCAS and SCLS. The SC has two input signals SX and SR, which map to microphone/loudspeaker for SCAS and line in/line out for SCLS. In principle, the SC works according to the following equation: if SX > SR + V then switch state
Therefore, SCAS controls the switching to transmit state and SCLS controls the switching to receive state. Switching is done only if SX exceeds SR by at least the expected acoustic level enhancement V which is divided into two parts: G and GD. A block diagram of the SC is shown in figure 17.
Log. Amp.
Peak Decrement PDS PDN
SX
Log. Amp.
Base Gain
Gain Reserve GDS GDN
Peak Decrement PDS PDN
SR
G
Figure 17 Speech Comparator - Block Diagram At both inputs, logarithmic amplifiers compress the signal range. Hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. The main task of the comparator is to control the echo. The internal coupling due to the direct sound and mechanical resonances are covered by G. The external coupling, mainly caused by the acoustic feedback, is controlled by GD/PD.
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PSB 4860
Functional Description The base gain (G) corresponds to the terminal couplings of the complete telephone: G is the measured or calculated level enhancement between both receive and transmit inputs of the SC. To control the acoustic feedback two parameters are necessary: GD represents the actual reserve on the measured G. Together with the Peak Decrement (PD) it simulates the echo behavior at the acoustic side: After speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. Till the end of that time (t) the level enhancement V must be at least equal to G to prevent clipping caused by these internal couplings. Then, only the acoustic feedback is present. This coupling, however, is reduced by air attenuation. For this in general the longer the delay, the smaller the echo being valid. This echo behavior is featured by the decrement PD.
dB GD* PD* GD
G
PD
RX-Speech
G
RX-noise
t Figure 18 Speech Comparator - Interdependence of Parameters
t
According to figure 18, a compromise between the reserve GD and the decrement PD has to be made: a smaller reserve (GD) above the level enhancement G requires a longer time to decrease (PD). It is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. In contrary, with a higher reserve (GD*) it is harder to overshout continuous speech or tones, but it enables a faster intercommunication because of a stronger decrement (PD*).
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PSB 4860
Functional Description Two pairs of coefficients, GDS/PDS when speech is detected, and GDN/PDN in case of noise, offer a different echo handling for speech and non-speech. With speech, even if very strong resonances are present, the performance will not be worsened by the high GDS needed. Only when speech is detected, a high reserve prevents clipping. A time period ET [ms] after speech end, the parameters of the comparator are switched to the "noise" values. If both sets of the parameters are equal, ET has no function. Table 5 G GDS PDS GDN PDN ET Speech Comparator Parameters Comment Base Gain Gain Reserve (Speech) Peak Decrement (Speech) Gain Reserve (Noise) Peak Decrement (Noise) Time to Switch from speech to noise parameters 1 1 1 1 1 1 - 48 to + 48 dB 0 to 48 dB 0.025 to 6 dB/ms 0 to 48 dB 0.025 to 6 dB/ms 0 to 992 ms
Parameter # of bytes Range
2.1.3.3
Attenuation Control
The attenuation control unit controls the attenuation stages GHX and GHR and performs state switching. The programmable attenuation ATT is completely switched to GHX (GHR) in receive state (transmit state). In idle state both GHX and GHR attenuate by ATT/2. In addition, attenuation is also influenced by the automatic gain control stages (AGCX, AGCR). State switching depends on the signals of one speech comparator and the corresponding speech detector. While each state is associated with the programmed attenuation, the time is takes to reach the steady-state attenuation after a state switch can be programmed (TSW). If the current state is either transmit or receive and no speech on either side has been detected for time TW then idle state is entered. To smoothen the transition, the attenuation is incremented (decremented) by DS until the evenly distribution ATT/2 for both GHX and GHR is reached. Table 6 shows the parameters for the attenuation unit. Note that TSW is dependent on the current attenuation by the formula T sw = SW x ATT .
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PSB 4860
Functional Description Table 6 TW ATT DS SW Attenuation Control Unit Parameters Comment TW to return to idle state Attenuation for GHX and GHR Decay Speed (to idle state) 1 1 1 1 16 ms to 4 s 0 to 95 dB 0.6 to 680 ms/dB
Parameter # of bytes Range
0.0052 to 10 ms/dB Decay Rate (used for TSW)
Note: In addition, attenuation is also influenced by the Automatic Gain Control stages (AGCX, AGCR) in order to keep the total loop attenuation constant.
2.1.3.4 Echo Suppression Status Output
The PSB 4860 can report the current state of the echo suppression unit to ease optimization of the parameter set of the echo suppression unit. In this case the SPS0 and SPS1 pins are set according to table 7. Table 7 SPS0 0 0 1 1 SPS Output Encoding SPS1 0 1 0 1 Echo Suppression Unit State no echo suppression operation receive transmit idle
Furthermore the controller can read the current value of the SPS pins by reading register SPSCTL. 2.1.3.5 Loudhearing
The speakerphone unit can also be used for controlled loudhearing. If enabled in loudhearing mode, the loudspeaker amplifier of the PSB 4851 (ALS) is used instead of GHR (figure 15) when appropriate to avoid oscillation. In order to enable this feature, the PSB 4851 must be programmed to allow ALS override. The ALS field within the AFE control register AFECTL defines the value sent to the PSB 4851 if attenuation is necessary (see specification of the PSB 4851). 2.1.3.6 Automatic Gain Control
The echo suppression unit has two identical automatic gain control units (AGCX, AGCR).
Semiconductor Group
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PSB 4860
Functional Description Operation of the AGC depends on a threshold level defined by the parameter COM (value relative to the maximum PCM-value). The regulation speed is controlled by SPEEDH for signal amplitudes above the threshold and SPEEDL for amplitudes below. Usually SPEEDH will be chosen to be at least 10 times faster than SPEEDL. The bold line in Figure 19 depicts the steady-state output level of the AGC as a function of the input level.
AGC input level
-20 dB
-10 dB
max. PCM
Example: COM = -30 dB AG_GAIN = 15 dB AG_ATT = 20 dB
-10 dB
AG_ATT
-20 dB
COM
AGC output level
AG_GAIN
Figure 19 Echo Suppression Unit - Automatic Gain Control For reasons of physiological acceptance the AGC gain is automatically reduced in case of continuous background noise (e.g. by ventilators). The reduction is programmed via the NOlS parameter. When the noise level exceeds the threshold determined by NOIS, the amplification will be reduced by the same amount the noise level is above the threshold. The current gain/attenuation of the AGC can be read at any time (AG_CUR). An additional low pass with time constant LP is provided to avoid an immediate response of the AGC to very short signal bursts. If SDX detects noise, AGCX is not working. In this case the last gain setting is used. Regulation starts with this value as soon as SDX detects speech. Likewise, if SDR detects noise, AGCR is not working. In this case the last gain setting is used. Regulation starts with this value as soon as SDR detects speech. When the AGC has been disabled the initial gain used immediately after enabling the AGC can be programmed. Table 8 shows the parameters of the AGC.
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PSB 4860
Functional Description Table 8 AG_INIT COM AG_ATT AG_CUR SPEEDL SPEEDH NOIS LP Automatic Gain Control Parameters Comment Initial AGC gain/attenuation Compare level rel. to max. PCM-value Attenuation range Gain range Current gain/attenuation Change rate for lower levels Change rate for higher levels Threshold for AGC-reduction by background noise AGC low pass time constant 1 1 1 1 1 1 1 1 -95 dB to 95dB 0 to - 95 dB 0 to -95 dB 0 to 95 dB -95 dB to 95 dB 0.25 to 62.5 dB/s 0.25 to 62.5 dB/s 0 to - 95 dB 0.025 to 16 ms
Parameter # of Bytes Range
AG_GAIN 1
Note: There are two sets of parameters, one for AGCX and one for AGCR. Note: By setting AG_GAIN to 0 dB a limitation function can be realized with the AGC.
2.1.3.7 Fixed Gain
Each signal path features an additional amplifier (LGAX, LGAR) that can be set to a fixed gain. These amplifiers should be used for the basic amplification in order to avoid saturation in the preceding stages. Table 9 shows the only parameter of this stage. Table 9 LGA 2.1.3.8 Fixed Gain Parameters Comment 1 -12 dB to 12 dB always active
Parameter # of Bytes Range
Mode Control
Table 10 shows the registers used to determine the signal sources and the mode. Table 10 Register SCTL SCTL SCTL SCTL Speakerphone Control Registers # of Bits 1 1 1 1 Name ENS ENC MD AGX Comment Echo suppression unit enable Echo cancellation unit enable Speakerphone or loudhearing mode AGCX enable
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PSB 4860
Functional Description Table 10 SCTL SCTL SCTL AFECTL SSRC1 SSRC1 SSRC2 SSRC2 Speakerphone Control Registers 1 1 1 4 5 5 5 5 AGR SDX SDR ALS I1 I2 I3 I4 AGCR enable SDX input tap SDR input tap ALS value for loudhearing Input signal 1 (microphone) Input signal 2 (microphone) Input signal 3 (line in) Input signal 4 (line in)
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PSB 4860
Functional Description 2.1.4 Line Echo Canceller
The PSB 4860 contains an adaptive line echo cancellation unit for the cancellation of near end echoes. The unit has two modes: normal and extended. In normal mode, the maximum echo length is 4 ms. This mode is always available. In extended mode, the maximum echo length is 24 ms. Extended mode cannot be used while the speech encoder, the echo cancellation unit or slow playback is active. The line echo cancellation unit is especially useful in front of the various detectors (DTMF, CPT, etc.). A block diagram is shown in figure 20. I2 + S15
Adaptive Filter I1 Figure 20 Line Echo Cancellation Unit - Block Diagram The line echo canceller provides only one outgoing signal (S15) as the other outgoing signal would be identical with the input signal I1. Input I2 is usually connected to the line input while input I1 is connected to the outgoing signal. In normal mode the adaption process can be controlled by three parameters: MIN, ATT and MGN. Adaption takes only place if both of the following conditions hold: 1. I1 > MIN 2. I1 - I2 - ATT + MGN > 0 With the first condition adaption to small signals can be avoided. The second condition avoids adaption during double talk. The parameter ATT represents the echo loss provided by external circuitry. The adaption stops if the power of the received signal (I2) exceeds the power of the expected signal (I1-ATT) by more than the margin MGN.
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PSB 4860
Functional Description Table 11 shows the registers associated with the line echo canceller. Table 11 Register LECCTL LECCTL LECCTL LECCTL LECLEV LECATT Line Echo Cancellation Unit Registers # of Bits Name Comment 1 1 5 5 15 15 EN MD I2 I1 MIN ATT MGN Line echo canceller enable Line echo canceller mode Input signal selection for I2 Input signal selection for I1 Minimal power for signal I1 Margin for double talk detection both both normal normal Relevant Mode both
Externally provided attenuation (I1 to I2) normal
LECMGN 15
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PSB 4860
Functional Description 2.1.5 DTMF Detector
Figure 21 shows a block diagram of the DTMF detector. The results of the detector are available in the status register and a dedicated result register that can be read via the serial control interface (SCI) by the external controller. All sixteen standard DTMF tones are recognized.
I1
DTMF Recognition
SCI
Figure 21 DTMF Detector - Block Diagram Table 12 to 14 show the associated registers. Table 12 DDCTL DDCTL DTMF Detector Control Register Name EN I1 Comment DTMF detector enable Input signal selection 1 5
Register # of Bits
As soon as a valid DTMF tone is recognized, the status word and the DTMF tone code are updated (table 13). Table 13 DTMF Detector Results Name DTV DTC Comment DTMF code valid DTMF tone code
Register # of Bits STATUS 1 DDCTL 5
DTV is set when a DTMF tone is recognized and reset when no DTMF tone is recognized or the detector is disabled. The code for the DTMF tone is placed into the register DDCTL. The registers DDTW and DDLEV hold parameters for detection (table 14). Table 14 Register DDTW DDLEV DTMF Detector Parameters # of Bits 15 6 Name TWIST MIN Comment Twist for DTMF recognition Minimum signal level to detect DTMF tones
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PSB 4860
Functional Description 2.1.6 CNG Detector
The calling tone (CNG) detector can detect the standard calling tones of fax machines or modems. This helps to distinguish voice messages from data transfers. The result of the detector is available in the status register that can be read via the serial control interface (SCI) by the external controller. The CNG detector consists of two band-pass filters with fixed center frequency of 1100 Hz and 1300 Hz.
CNG Detector
I1 1100 Hz 1300 Hz SCI
Figure 22 CNG Detector - Block Diagram Table 15 shows the available parameters. Table 15 Register CNGCTL CNGCTL CNGLEV CNGBT CNGRES CNG Detector Registers # of Bits 1 5 16 16 16 Name EN I1 MIN TIME RES Comment CNG detector enable Input signal selection Minimum signal level Minimum time of signal burst Input signal resolution
Both the programmed minimum time and the minimum signal level must be exceeded for a valid CNG tone. Furthermore the input signal resolution can be reduced by the RES parameter. This can be useful in a noisy environment at low signal levels although the accuracy of the detection decreases. As soon as a valid tone is recognized, the status word of the PSB 4860 is updated. The status bits are defined as follows: Table 16 CNG Detector Result Name CNG Comment Fax/Modem calling tone detected
Register # of Bits STATUS 1
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Functional Description 2.1.7 Alert Tone Detector
The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for caller id protocols. The results of the detector are available in the status register and the dedicated register ATDCTL0 that can be read via the serial control interface (SCI) by the external controller.
Alert Tone
I1
Detector
SCI
Figure 23 Alert Tone Detector - Block Diagram
Table 17 Register ATDCTL0 ATDCTL0 ATDCTL1 ATDCTL1 ATDCTL1
Alert Tone Detector Registers # of Bits 1 5 1 1 8 Name EN I1 MD DEV MIN Comment Alert Tone Detector Enable Input signal selection Detection of dual tones or single tones Maximum deviation (0.5% or 1.1%) Minimum signal level to detect alert tones
As soon as a valid alert tone is recognized, the status word of the PSB 4860 and the code for the detected combination of alert tones are updated (table 18). Table 18 Register STATUS ATDCTL0 Alert Tone Detector Results # of Bits Name 1 2 ATV ATC Comment Alert tone detected Alert tone code
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Functional Description 2.1.8 CPT Detector
The selected signal is monitored continuously for a call progress tone. The CPT detector consists of a band-pass and an optional timing checker (figure 24).
Band-pass
I1 300-640 Hz SCI (Status)
Timing Checker
Figure 24 CPT Detector - Block Diagram The CPT detector can be used in two modes: raw and cooked. In raw mode, the occurrence of a signal within the frequency range, time and energy limits is directly reported. The timing checker is bypassed and therefore the PSB 4860 does not interpret the length or interval of the signal. In cooked mode, the number and duration of signal bursts are interpreted by the timing checker. A signal burst followed by a gap is called a cycle. Cooked mode requires a minimum of two cycles. The CPT flag is set with the first burst after the programmed number of cycles has been detected. The CPT flag remains set until the unit is disabled, even if the conditions are not met anymore. In this mode the CPT is modelled as a sequence of identical bursts separated by gaps with identical length. The PSB 4860 can be programmed to accept a range for both the burst and the gap. It is also possible to specify a maximum aberration of two consecutive bursts and gaps. Figure 25 shows the parameters for a single cycle (burst and gap).
tBmax tBmin
tGmin tGmax
Figure 25 CPT Detector - Cooked Mode The status bit is defined as follows:
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Functional Description Table 19 CPT Detector Result Name CPT Comment CP tone currently detected [340 Hz; 640 Hz]
Register # of Bits STATUS 1
CPT is not affected by reading the status word. It is automatically reset when the unit is disabled. Table 20 shows the control register for the CPT detector. Table 20 Register CPTCTL CPTCTL CPTCTL CPTMN CPTMN CPTMX CPTMX CPTDT CPTDT CPTTR CPTTR CPTTR CPT Detector Registers # of Bits Name 1 1 5 8 8 8 8 8 8 3 8 4 EN MD I1 MINB MING MAXB MAXG DIFB DIFG NUM MIN SN Comment Unit enable Mode (cooked, raw) Input signal selection Minimum time of a signal burst (tBmin) Minimum time of a signal gap (tGmin) Maximum time of a signal burst (tBmax) Maximum time of a signal gap (tGmax) Maximum difference between consecutive bursts Maximum difference between consecutive gaps Number of cycles (cooked mode), 0 (raw mode) Minimum signal level to detect tones Minimal signal-to-noise ratio
If any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst.
Note: In cooked mode CPT is set with the first burst after the programmed number of cycles has been detected. Note: The number of cycles must be set to zero in raw mode.
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Functional Description 2.1.9 Caller ID Decoder
The caller ID decoder is basically a 1200 baud modem (FSK, demodulation only). The bit stream is formatted by a subsequent UART and the data is available in a data register along with status information (figure 26).
I1
FSK demod.
(Bellcore, V.23)
UART
SCI (Status, Data)
Figure 26 Caller ID Decoder - Block Diagram The FSK demodulator supports two modes according to table 21. The appropriate mode is detected automatically. Table 21 Mode 1 2 Caller ID Decoder Modes Mark (Hz) 1200 1300 Space (Hz) 2200 2100 Comment Bellcore V.23
The CID decoder does not interpret the data received. Each byte received is placed into the CIDCTL register (table 23). The status byte of the PSB 4860 is updated (table 22). Table 22 Caller ID Decoder Status Name CIA CD Comment CID byte received Carrier Detected
Register # of Bits STATUS 1 STATUS 1
CIA and CD are cleared when the unit is disabled. In addition, CIA is cleared when CIDCTL0 is read. Table 23 Register CIDCTL0 CIDCTL0 CIDCTL0 Caller ID Decoder Registers # of Bits Name 1 5 8 EN I1 DATA Comment Unit enable Input signal selection Last CID data byte received
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Functional Description Table 23 Register CIDCTL1 CIDCTL1 CIDCTL1 Caller ID Decoder Registers # of Bits Name 5 6 5 NMSS NMB MIN Comment Number of mark/space sequences necessary for successful detection of carrier detect Number of mark bits necessary before space of first byte after carrier detect Minimum signal level for CID detection
When the CID unit is enabled, it first waits for a channel seizure signal consisting of a series of alternating space and mark signals. The number of spaces and marks that have to be received without errors before the PSB 4860 reports a carrier detect by setting status bit CD can be programmed. Channel seizure must be followed by at least 16 continuous mark signals. The first space signal detected is then regarded as the start bit of the first message byte. The interpretation of the data, including message type, length and checksum is completely left to the controller. The CID unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself.
Note: Some caller ID mechanism may require additional external components for DC decoupling. These tasks must be handled by the controller. Note: The controller is responsible for selecting and storing parts of the CID as needed.
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Functional Description 2.1.10 DTMF Generator
The DTMF generator can generate single or dual tones with programmable frequency and gain. This unit is primarily used to generate the common DTMF tones but can also be used for signalling or other user defined tones. A block diagram is shown in figure 27.
f1 generator
gain1
att1
S9
f2 generator
gain2
att2
S10
Figure 27 DTMF Generator - Block Diagram Both generators and amplifiers are identical. There are two modes for programming the generators, cooked mode and raw mode. In cooked mode, the standard DTMF frequencies are generated by programming a single 4 bit code. In raw mode, the frequency of each generator/amplifier can be programmed individually by a separate register. The unit has two outputs which provide the same signal but with individually programmable attenuation. Table 24 shows the parameters of this unit. Table 24 DGCTL DGCTL DGCTL DGF1 DGF2 DGL DGL DGATT DGATT DTMF Generator Registers Name EN MD DTC FRQ1 FRQ2 LEV1 LEV2 ATT1 ATT2 Comment Enable for generators Mode (cooked/raw) DTMF code (cooked mode) Frequency of generator 1 Frequency of generator 2 Level of signal for generator 1 Level of signal for generator 2 Attenuation of S9 Attenuation of S10 1 1 4 15 15 7 7 8 8
Register # of Bits
Note: DGF1 and DGF2 are undefined when cooked mode is used and must not be written.
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Functional Description 2.1.11 Speech Coder
The speech coder (figure 28) has two input signals I1 and I2. The first signal (I1) is fed to the coder while the second signal (I2) is used as a reference signal for voice controlled recording. The signal I1 can be coded by either a High Quality coder or a Long Play coder.
I1 MIN
HQ 10300 bit/s Memory
I2
LP
LP 3300 bit/s
Figure 28 Speech Coder - Block Diagram In High Quality the output data stream runs at a fixed rate of 10300 bit/s and provides excellent speech quality. In Long Play mode, the output data stream is further reduced to an average of 3300 bit/s while still maintaining good quality. Data is written starting at the current file pointer and the file pointer is advanced as needed. In case of any memory error (e.g. memory full) a file error is indicated and the coder is disabled. The controller must subsequently close the file. The coder can be switched on the fly. However, it may take up to 60 ms until the switch is executed. The controller must therefore wait for at least this time until issuing another command that relies on the mode switch. No audio data is lost during switching. The signal I2 is first filtered by a low pass LP1 with programmable time constant and then compared to a reference level MIN. If the filtered signal exceeds MIN, then the status bit SD (table 25) is set immediately. If the filtered signal has been smaller than MIN for a programmable time TIME then the status bit SD is reset. The coder can be enabled in permanent mode or in voice recognition mode. In permanent mode, the coder starts immediately and compresses all input data continuously. The current state of the status bit SD does not affect the coder. In voice recognition mode, the coder is automatically started on the first transition of the status bit from 0 to 1. Once the coder has started it remains active until disabled. Table 25 Speech Coder Status Name SD Comment Speech detected
Register # of Bits STATUS 1
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Functional Description The operation of the speech coder is defined according to table 26. Table 26 SCCTL SCCTL SCCTL SCCTL SCCTL SCCT2 SCCT2 SCCT3 Speech Coder Registers Name EN HQ VC I1 I2 MIN TIME LP Comment Enable speech coder High quality mode Voice controlled recording Input signal 1 selection Input signal 2 selection Minimal signal level for speech detection Minimum time for reset of SD Time constant for low-pass 1 1 1 5 5 8 8 8
Register # of Bits
Note: The peak data rate in LP mode is 4800 bit/s. Note: Both HQ and LP mode will not produce identical bit streams after a coding/ decoding cycle.
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Functional Description 2.1.12 Speech Decoder
The speech decoder (figure 29) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream.
HQ 10300 bit/s Memory S13 LP 3300 bit/s
Figure 29 Speech Decoder - Block Diagram The decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent of the selected quality. The decoder requests input data as needed at a variable rate. Table 27 shows the signal and mode selection for the speech decoder. Table 27 SDCTL SDCTL Speech Decoder Registers Name EN SPEED Comment Enable speech decoder Selection of playback speed 1 2
Register # of Bits
Data reading starts at the location of the current file pointer. The file pointer is updated during speech decoding. If the end of the file is reached, the decoder is automatically disabled. The PSB 4860 automatically resets SDCTL:EN at this point.
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Functional Description 2.1.13 Analog Front End Interface
There are two identical interfaces at the analog side (to PSB 4851) as shown in figure 30.
Channel 1
S2
I1 I2 I3
Channel 2
S4
I1 I2 I3
line out
IG2
loudspeaker
IG4
line in
IG1
HP
S1
microphone
IG3
HP
S3
Figure 30 Analog Front End Interface - Block Diagram For each signal an amplifier is provided for level adjustment. The incoming signals can be passed through an optional high-pass (HP). This high-pass (fg=20 Hz) is useful for blocking DC offsets and should be enabled by default. Furthermore, up to three signals can be mixed in order to generate the outgoing signals (S2,S4). Table 28 shows the associated registers. Table 28 IFG1 IFG2 IFS1 IFS1 IFS1 IFS1 IFG3 IFG4 IFS2 IFS2 IFS2 IFS2 Analog Front End Interface Registers Name IG1 IG2 HP I1 I2 I3 IG3 IG4 HP I1 I2 I3 Comment Gain for IG1 Gain for IG2 High-pass for S1 Input signal 1 for IG2 Input signal 2 for IG2 Input signal 3 for IG2 Gain for IG3 Gain for IG4 High-pass for S3 Input signal 1 for IG4 Input signal 2 for IG4 Input signal 3 for IG4 16 16 1 5 5 5 16 16 1 5 5 5
Register # of Bits
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Functional Description 2.1.14 Digital Interface
There are two almost identical interfaces at the digital side as shown in figure 31. The only difference between these two interfaces is that only channel 1 supports the SSDI mode.
Channel 1 (SSDI/IOM(R)-2 Interface)
I1
Channel 2 (IOM(R)-2 Interface)
I1
S6
I2
S8
I2
ATT1
I3
ATT2
I3
HP
S5
HP
S7
Figure 31 Digital Interface - Block Diagram Each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (ATT). The attenuator can be used for artificial echo if there is none externally provided (e.g. ISDN application). Each input can be passed through an optional high-pass (HP). The associated registers are shown in table 29. Table 29 IFS3 IFS3 IFS3 IFS3 IFS4 IFS4 IFS4 IFS4 Digital Interface Registers Name I1 I2 I3 HP I1 I2 I3 HP Comment Input signal 1 for S6 Input signal 2 for S6 Input signal 3 for S6 High-pass for S5 Input signal 1 for S8 Input signal 2 for S8 Input signal 3 for S8 High-pass for S7 5 5 5 1 5 5 5 1
Register # of Bits
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Functional Description Table 29 IFG5 IFG5 Digital Interface Registers Name ATT1 ATT2 Comment Attenuation for input signal I3 (Channel 1) Attenuation for input signal I3 (Channel 2) 8 8
Register # of Bits
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Functional Description 2.1.15 Universal Attenuator
The PSB 4860 contains an universal attenuator that can be connected to any signal (e.g. for sidetone gain in ISDN applications).
I1
UA
S14
Figure 32 Universal Attenuator - Block Diagram Table 30 shows the associated register. Table 30 UA UA Universal Attenuator Registers Name ATT I1 Comment Attenuation for UA Input signal for UA 8 5
Register # of Bits
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Functional Description 2.1.16 Automatic Gain Control Unit
In addition to the universal attenuator with programmable but fixed gain the PSB 4860 contains an amplifier with automatic gain control (AGC). The AGC is preceeded by a signal summation point for two input signals. One of the input signals can be attenuated.
I1
AGC
S16
I2
ATT
S17
Figure 33 Automatic Gain Control Unit - Block Diagram Furthermore the signal after the summation point is available. Besides providing a general signal summation (S16 not used) this signal is especially useful if the AGC unit provides the input signal for the speech coder. In this case S17 can be used as a reference signal for voice controlled recording. The operation of the AGC is similar to AGCX (ACCR) of the speakerphone. The differences are as follows: * No NOIS parameter * Separate enable/disable control * Slightly different coefficient format Furthermore the AGC contains a comparator that starts and stops the gain regulation. The signal after the summation point (S17) is filtered by a peak detector with time constant DEC for decay. Then the signal is compared to a programmable limit LIM. Regulation takes only place when the filtered signal exceeds the limit. Table 31 shows the associated registers. Table 31 Automatic Gain Control Registers Name EN I1 I2 ATT AG_INIT COM Comment Enable Input signal 1 for AGC Input signal 2 for AGC Attenuation for I2 Initial AGC gain/attenuation Compare level rel. to max. PCM-value
Register # of Bits AGCCTL 1 AGCCTL 5 AGCCTL 5 AGCATT 15 AGC1 AGC1 8 8
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Functional Description Table 31 AGC2 AGC2 AGC3 AGC3 AGC4 AGC4 AGC5 Automatic Gain Control Registers Name SPEEDL SPEEDH AG_ATT AG_GAIN DEC LIM LP Comment Change rate for lower levels Change rate for higher level Attenuation range Gain range Peak detector time constant Comparator minimal signal level AGC low pass time constant 8 8 8 7 7 8 7
Register # of Bits
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Functional Description 2.1.17 Equalizer
The PSB 4860 also provides an equalizer that can be inserted into any signal path. The main application for the equalizer is the adaption to the frequency characteristics of the microphone, transducer or loudspeaker. The equalizer consists of an IIR filter followed by an FIR filter as shown in figure 34.
I
z-1
z-1
z-1
z-1
z-1
z-1
IIR
A1
A2
A9
B9
B2
C1
z-1
z-1
z-1
FIR
D1
D2
D17
S18
C2
Figure 34 Equalizer - Block Diagram The coefficients A1-A9, B2-B9 and C1 belong to the IIR filter, the coefficients D1-D17 and C2 belong to the FIR filter. Table 32 shows the registers associated with the equalizer. Table 32 FCFCTL FCFCTL FCFCTL Equalizer Registers Name EN I ADR Comment Enable Input signal for equalizer Filter coefficient address Filter coefficient data 1 5 6
Register # of Bits
FCFCOF 16
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Functional Description Due to the multitude of coefficients the uses an indirect addressing scheme for reading or writing an individual coefficient. The address of the coefficient is given by ADR and the actual value is read or written to register FCFCOF. In order to ease programming the PSB 4860 automatically increments the address ADR after each access to FCFCOF.
Note: Any access to an out-of-range address automatically resets FCFCTL:ADR.
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Functional Description 2.2
Memory Management Memory Management - General
Memory Management
This section describes the memory management provided by the PSB 4860. As figure 35 shows, three units can access the external memory. During recording, the speech coder can write compressed speech data into the external memory. For playback, the speech decoder reads compressed speech data from external memory. In addition, the microcontroller can directly access the memory by the SCI interface.
Speech Decoder
SCI
Memory
Speech Coder
Figure 35 Memory Management - Data Flow The memory is organized as a file system. For each memory space (R/W-memory and voice prompt memory) the PSB 4860 maintains a directory with 255 file descriptors (figure 36).
directory
file descriptor 1
file descriptor (R/W)
length (0-65535) user data (16 bits)
file descriptor n RTC1 (16 bits) RTC2 (16 bits) file descriptor 255
Figure 36 Memory Management - Directory Structure The directories must be created after each power failure for volatile R/W-memory. All file descriptors are cleared (all words zero). For non-volatile memory, the directories have to
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Functional Description be created only once. If the directories already exist, the memory has just to be activated after a reset. The file descriptors are not changed in this case. All commands that access the other fields or involve a write access must not be used in voice prompt memory space. 2.2.1 File Definition and Access
A file is a linear sequence of units and can be accessed in two modes: binary and audio. In binary mode, a unit is a word. In audio mode, a unit is a variable number of words representing 30 ms of uncompressed speech. A file can contain at most 65535 units. Figure 37 shows an audio file containing 100 audio units. The length of the message is therefore 3 s.
3s
Hi Jack, this is Tom. Please call me back tomorrow.
0 99
Figure 37 Audio File Organization - Example Figure 38 shows a binary file of 11 words containing a phonebook (with only two entries).
TO
M
55
54
30
J
AC
K
55
58
11
544F 4D20 3535 3534 3330 004A 4143 4B20 5555 5538 3131
0
1
10
Figure 38 Binary File Organization - Example There is one special file in the voice prompt directory (referenced by file number 255) which is intended for a large number of phrases and hence has a different organization.This file exists only in the directory for the voice prompt memory. It consists of up to 2048 phrases of arbitrary individual length. The actual number of units within an individual phrase is determined during creation and cannot be altered afterwards. Phrases can be combined in any sequence without intermediate noise or gaps.
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Functional Description Figure 39 shows a phrase file containing a total of five phrases.
you have messages left one two friday 0 1 4
Figure 39 Phrase File Organization - Example Before an access to a file can take place, the file must be opened with the following information: 1. memory space 2. file number 3. access mode These parameters remain effective until the next open command is given or, in case of the file pointer, until a file access. All other files are closed and cannot be accessed. The file with file number 0 is not a physical file. Opening this file closes all physical files. The PSB 4860 provides four registers for file access and two bits within the STATUS register. Table 33 shows these registers. Table 33 FCMD FCTL FDATA FPTR Memory Management Registers Comment Command to execute Access mode and file number Data transfer and additional parameters File pointer (phrase selector) Busy and Error indication 16 16 16 16 (11)
Register # of Bits
STATUS 16
The status register contains two flags (table 34) to indicate if currently a file command is under execution and if the last file command terminated without error. A new command must not be written to FCMD while the last one is still running (STATUS:BSY=1). The only command that can be aborted is Compress File. Table 34 Memory Management Status Name BSY ERR Comment File command or decoder/encoder still running File command completed/aborted with error
Register # of Bits STATUS 1 STATUS 1
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Functional Description Writing to FCMD also resets the error bit in the status register. Table 35 shows the parameters defining the access mode and the access location. All parameters can only be written when no file command is currently running. They become effective after the completion of an open command. If another unit (e.g. speech coder) accesses the file, the file pointer is updated automatically. Therefore the controller can monitor the progress of recording or playing by reading the file pointer. Table 35 FCTL FCTL FCTL FCTL FPTR Memory Management Parameters Name MS MD TS FNO Comment Memory space (R/W or voice prompt) Access mode (audio or binary) Write timestamp (file open only) File number (active file) File pointer or phrase selector 1 1 1 8 16
Register # of Bits
Commands are written to the FCMD register. The busy bit in the STATUS register is set within 125s. The command may start execution after a delay, however (see section 2.2.5). Some commands require additional parameters which are written prior to the command into the specified registers. Data transfer is done by the register FDATA (both reading and writing). 2.2.2 User Data Word
The user data word consists of 12 bits that can be read or written by the user, two bits (R) that are reserved for future use and two read-only bits (D,M) which indicate the status of a file. 15
D M R R User Definable
0
If D is set, the file is marked for deletion and should not be used any more. This bit is maintained by the PSB 4860 for housekeeping.
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Functional Description 2.2.3 High Level Memory Management Commands
This section describes each of the high level memory management commands in detail. These commands are sufficient for normal operation of an answering machine. In addition, there are four low level commands (section 2.2.4). These commands are only required for special tasks like in-system reprogramming of the voice prompt area.
Memory Management - Commands
2.2.3.1
Initialize
This command creates a directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. The PSB 4860 can either create an empty directory from scratch or leave the first n files of an existing directory untouched while deleting the remaining files (ARAM/DRAM only). This option is useful if due to an unexpected event (e.g. power loss during recording) some data is corrupted. In that case vital system information can still be recovered if it has been stored in the first files. Table 36 FCMD FCMD FCTL Initialize Memory Parameters Name CMD IN FNO Comment Initialize command code Confirmation for Initialization 0: delete no file 1: delete all files n: delete starting with file n Type of R/W memory (DRAM, Flash) Quality of R/W memory (Audio, Normal) Scan for voice prompt directory 5 1 8
Register # of Bits
CCTL CCTL CCTL
2 1 1
MT MQ MV
Table 37 FDATA
Initialize Memory Results Name Comment Number of usable 1kByte blocks in R/W memory 16
Register # of Bits
Possible Errors: * no R/W memory found * more than 59 bad blocks (flash and ARAM) * voice prompt directory requested, but not detected
Note: This command must be given only once for flash devices.
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Functional Description 2.2.3.2 Activate
This command activates an existing directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. Upon activation the PSB 4860 checks (in case of ARAM/DRAM only) the consistency of the directory in R/W memory space. It returns the first file that contains corrupted data (if any). If corrupted data is detected an initialization should be performed with the same file number as an input parameter. Table 38 FCMD CCTL CCTL CCTL Activate Memory Parameters Name CMD MT MQ MV Comment Activate command code Type of R/W memory (DRAM, Flash) Quality of R/W memory (Audio, Normal) Voice prompt directory available 5 2 1 1
Register # of Bits
Table 39 FDATA FCTL
Activate Memory Results Name FNO Comment Number of usable 1 kByte blocks in R/W memory n: number of first corrupted file 16 8
Register # of Bits
Possible error conditions: * * * * * no memory connected no directory found device ID wrong (flash only) corrupted files found (see FCTL:FNO) directory corrupted
This command can have three types of result as shown in table 40. Table 40 Result no error soft error Activate Memory Result Interpretation STATUS: FCTL: ERR FNO 0 1 0 n 1 Comment Command successful, memory activated. The first n-1 files are O.K. The memory is activated. The memory is not activated due to a hard error.
hard error 1
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Functional Description 2.2.3.3 Open File
A specific file is opened for subsequent accesses with the specified access mode. Opening a new file automatically closes the currently open file and clears the file pointer. Opening file number 0 can be used to close all physical files. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. Table 41 FCMD FCTL FCTL FCTL FCTL Open File Parameters Name CMD MS MD TS FNO Comment Open command code Memory space (R/W, voice prompt) Access mode (audio or binary) Write timestamp File number 5 1 1 1 8
Register # of Bits
Possible error conditions: * * * * * selected file marked for deletion, but not yet deleted by garbage collection memory space invalid new file selected, but memory full exceeds number of prompts (in voice prompt space only) wrong access mode selected for existing file
Note: In case of flash memory existing ones in the entries RTC1/RTC2 of the file descriptor cannot be altered. Therefore TS should be set only once during the lifetime of a file.
2.2.3.4 Open Next Free File
The next free file is opened for subsequent write accesses with the specified access mode. The search starts at the specified file number. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. If a free file has been found, the file is opened and the file number is returned in FCTL:FNO. Otherwise an error is reported. Table 42 FCMD FCTL Open Next Free File Parameters Name CMD MD Comment Open Next Free File command code Access mode (audio or binary) 5 1
Register # of Bits
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Functional Description Table 42 FCTL FCTL
:
Open Next Free File Parameters Name TS FNO Comment Write timestamp Starting point (>0) 1 8
Register # of Bits
Table 43 FCTL
Open Next Free File Results Name FNO Comment File number 8
Register # of Bits
Possible error conditions: * no unused file found * memory full
Note: In case of flash memory existing ones cannot be altered. Therefore TS should be set only once during the lifetime of a file. Note: R/W-memory must be selected. Otherwise the result is unpredictable.
2.2.3.5
Seek
The file pointer of the currently opened file is set to the specified position. If the current file is the phrase file the PSB 4860 starts the speech decoder immediately after the seek is finished. This is done by simply enabling the decoder. All other settings of the decoder remain unaffected. The BSY bit is first set during the file command. It is then reset for a short period until the speech decoder is enabled internally. It is then set again while the decoder is running and finally reset when the phrase is finished. Table 44 FCMD FPTR Seek Parameters Name CMD Comment Seek command code File pointer (phrase selector) 5 16 (11)
Register # of Bits
Possible error conditions: * file pointer out of range * phrase number out of range
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Functional Description 2.2.3.6 Cut File
All units starting with the unit addressed by the file pointer are removed from the file. If all units are deleted the file is marked for deletion (see user data word). However, the associated file descriptor and memory space are released only after a subsequent garbage collection. Table 45 FCMD FPTR Cut File Parameters Name CMD Comment Cut command code Position of first unit to delete 5 16
Register # of Bits
Possible error conditions: * file pointer out of range * voice prompt memory selected 2.2.3.7 Compress File
An audio file that has been recorded in HQ mode can be recoded using LP mode. This reduces the file size to approximately one third of the original size. The speech quality, however, is somewhat lower compared to a signal that has been recorded in LP mode in the first place. This command can be aborted at any time and resumed later without loss of information. Prior to this command all files must be closed. Table 46 shows the parameters for this command.
.
Table 46 FCMD FCTL
Compress File Parameters Name CMD FNO Comment Compress command code File number 5 8
Register # of Bits
Possible error conditions: * invalid * another file currently open * binary file selected
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Functional Description 2.2.3.8 Memory Status
This command returns the number of available 1 kB blocks in R/W memory space. Table 47 FCMD Memory Status Parameters Name CMD Comment Memory status code 5
Register # of Bits
Table 48 FDATA
Memory Status Results Name FREE Comment Number of free blocks 16
Register # of Bits
Possible error conditions: * file open 2.2.3.9 Garbage Collection
This command initiates a garbage collection. Until a garbage collection files that are marked for deletion still occupy the associated file descriptor and memory space. After the garbage collection these file descriptors and the associated memory space are available again. This command can optionally remap the directory. In this mode the remaining file descriptors are remapped to form a contiguous block starting with file number 1. The original order is preserved. This command requires that all files are closed, i.e. file 0 is opened. Independently of the selected directory only the read/write directory is used. Table 49 FCMD FCMD Garbage Collection Parameters Name CMD RD Comment Garbage Collection Command Code Remap Directory 5 1
Register # of Bits
Possible error conditions: * file open 2.2.3.10 Access File Descriptor
By this command the length, user data word and RTC1/RTC2 of a file descriptor can be read. The user data word can also be written. The file or the other entries of the file descriptor are not affected by this command.
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Functional Description Table 50 FCMD FDATA Access File Descriptor Parameters Name CMD Comment Read Access or Write Access command code User data (write access only) 5 16
Register # of Bits
Table 51 FDATA
Access File Descriptor Results Name Comment Content of selected entry (read access only) 16
Register # of Bits
Possible error conditions: * none
Note: In case of flash memory bits already set to 1 cannot be altered. Note: Do not use this command with the phrase file (fno = 255).
2.2.3.11 Read Data
This command can be used in binary access mode only. A single word is read at the position given by the file pointer. The file pointer can be set by the Seek command. The file pointer is advanced by one word automatically. Table 52 FCMD Read Data Parameters Name CMD Comment Read Data Command Code 5
Register # of Bits
Table 53 FDATA
Read Data Results Name Comment Data word 16
Register # of Bits
Possible error conditions: * file pointer out of range * phrase file selected * audio file selected
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Functional Description 2.2.3.12 Write Data
This commands can be used in binary access mode only. A single word is written at the position of the file pointer. The file pointer is advanced by one word automatically. Note, that for FLASH memory only zeroes can be overwritten by ones. This restriction occurs only if an already used value within an existing file is to be overwritten. Table 54 FCMD FDATA Write Data Parameters Name CMD Comment Access Mode Command Code (including mode) Data word 5 16
Register # of Bits
Possible error conditions: * * * * file pointer out of range (for existing files only) voice prompt memory selected memory full audio file selected
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Functional Description 2.2.4 Low Level Memory Management Commands
These commands allow the direct access of any location (single word) of the external memory. Additionally it is possible to erase any block in case of a flash device. These commands should not be used during normal operation as they may interfere with the file system. No file must be open when one of these commands is given. The primary use of these commands is the in-system programming of a flash device with voice prompts. Please refer to the appropriate Application Notes. 2.2.4.1 Set Address
This command sets the 24 bit address pointer APTR. Only the address bits A8-A23 are set, the address bits A0-A7 are automatically cleared. Table 55 FCMD FDATA Set Address Parameters Name CMD ADR Comment Set Address command code Address bits A8-A23 of address pointer APTR 5 16
Register # of Bits
Possible error conditions: * file open 2.2.4.2 DMA Read
This command reads a single word addressed by APTR. After the read access APTR is automatically incremented by one. Table 56 shows the parameters for this command. Table 56 FCMD DMA Read Parameters Name CMD Comment DMA Read command code 5
Register # of Bits
Table 57 FDATA
DMA Read Results Name DATA Comment Data read from address APTR. 16
Register # of Bits
Possible error conditions: * file open
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Functional Description 2.2.4.3 DMA Write
This command writes a single word to the location addressed by APTR. After the write access APTR is automatically incremented by one. Table 58 shows the parameters for this command. Table 58 FCMD FDATA DMA Write Parameters Name CMD DATA Comment DMA Write command code Data to be written to APTR 5 16
Register # of Bits
Possible error conditions: * file open
Note: If flash memory is connected the actual write is only performed when the last word within a page is written. Until then the data is merely buffered in the flash device. Please check the flash memory data sheets on page size.
2.2.4.4 Block Erase
This command erases the physical block which includes the address given by APTR. The actual amount of memory erased by this command depends on the block size of the flash device. Table 59 shows the parameters for this command. Table 59 FCMD Block Erase Parameters Name CMD Comment Block Erase command code 5
Register # of Bits
Possible error conditions: * file open * ARAM/DRAM configured
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Functional Description 2.2.5 Execution Time
The execution time of the file commands is determined by four factors: 1. Internal state of the PSB 4860 2. Memory configuration 3. Memory state 4. Individual characteristics of the memory devices Therefore there is no general formula for an exact calculation of the execution time for file commands. For ARAM/DRAM items three and four are not significant as the memory access timing is always fixed and no additional delay is incurred for erasing memory blocks. However, the amount of memory has significant impact on the initialization in case of ARAM and flash. For flash devices the particular location of a write access in combination with the internal organization of the memory device may result in a block erase and subsequent write accesses in order to copy data. In this case the individual erase and write timing of the attached devices also prolongs the execution time. The first factor, the internal state of the PSB 4860, can influence all file commands regardless of the memory type attached. In general the PSB 4860 may delay any file command by up to 30 ms. However, it is possible to skip this delay if the following conditions hold: 1. The command is not initialize/activate 2. Neither the DTMF detector nor the speech coder nor the speech decoder are running If neither condition is violated then the PSB 4860 can be forced to start command execution immediately. This is done by setting the EIE bit in the FCMD register along with the command code. Table 60 gives an indication of the execution time for two typical memory configurations. Table 60 Command Initialize Activate Open File /Open Next Free File Seek (within 4 MBit File) Seek (within phrase file) Cut File Compress File Access File Descriptor
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Execution Times ARAM (4 MBit) KM29LV040 40 s1) < 10 ms <10 ms <0.5 s <1 ms <5 ms #units * 30 ms <10 ms <11 s 3s <26 ms <0.5 s <1 ms <5 ms #units * 30 ms <10 ms
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Functional Description Table 60 Command Memory Status Read/Write Data Garbage Collection
1)
Execution Times ARAM (4 MBit) KM29LV040 <10 ms <10 ms <20 ms <10 ms <10 ms 3s
less than 20 ms for DRAM
2.2.6
Special Notes on File Commands
1. No MMU commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. Therefore reading or writing the file descriptor is only allowed after all data writing has happened. 2. If an audio file has been opened for replay, a Write File Descriptor Command must be followed by a Seek command before the decoder can be enabled.
Semiconductor Group
78
10.97
PSB 4860
Functional Description 2.3
Miscellaneous Miscellaneous
Miscellaneous Real Time Clock
2.3.1
The PSB 4860 supplies a real time clock which maintains time with a resolution of a second and a range of up to a year. There are two registers which contain the current time and date (table 61). Table 61 RTC1 RTC1 RTC2 RTC2 Real Time Clock Registers Name SEC MIN HR DAY Comment Seconds elapsed Minutes elapsed Hours elapsed Days elapsed 6 6 5 11
Register # of Bits
The real time clock maintains time during normal mode and power down mode only if the auxiliary oscillator OSC is running and the RTC is enabled.
Note: Writing out-of-range values to RTC1 and RTC2 results in undefined operation of the RTC
2.3.2 SPS Control Register
The two SPS outputs (SPS0, SPS1) can be used as either general purpose outputs, speakerphone status outputs, extended address outputs for Voice Prompt EPROM or as status register outputs. Table 62 shows the associated register. Table 62 SPSCTL SPSCTL SPSCTL SPSCTL SPS Registers 1 1 3 4 SP0 SP1 MODE POS Output Value of SPS0 Output Value of SPS1 Mode of Operation Position for status register window
When used as status register outputs, the status register bit at position POS appears at SPS0 and the bit at position POS+1 appears at SPS1. This mode of operation can be used for debugging purposes or direct polling of status register bits. 2.3.3 Reset and Power Down Mode
The PSB 4860 can be in either reset mode, power down mode or active mode. During reset the PSB 4860 clears the hardware configuration registers and stops both internal
Semiconductor Group 79 10.97
PSB 4860
Functional Description and external activity. The address lines MA0-MA15 provide a weak low until they are actually used as address lines (strong outputs) or auxiliary port pins (I/O). In reset mode the hardware configuration registers can be read and written. With the first access to a read/write register the PSB 4860 enters active mode. In this mode the main oscillator is running and normal operation takes place. By setting the power down bit (PD) the PSB 4860 can be brought to power down mode. Table 63 CCTL Power Down Bit Name PD Comment power down mode 1
Register # of Bits
In power down mode the main oscillator is stopped and, depending on HWCONFIG2:PPM), the memory control lines are released (weak high). Depending on the configuration (ARAM/DRAM, APP) the PSB 4860 may still generate external activity (e.g. refresh cycles). The PSB 4860 enters active mode again upon an access to a read/ write register. Figure 40 shows a state chart of the modes of the PSB 4860.
Reset Mode R/W reg. access RST=1 RST=1
CCTL.PD=1 Active Mode R/W reg. access Power Down Mode
Figure 40 Operation Modes - State Chart 2.3.4 Interrupt
The PSB 4860 can generate an interrupt to inform the host of an update of the STATUS register according to table 64. An interrupt mask register (INTM) can be used to disable or enable the interrupting capability of each bit of the STATUS register except ABT individually.
Semiconductor Group
80
10.97
PSB 4860
Functional Description Table 64 STATUS (old) RDY=0 CIA=0 CD=0 CD=1 CPT=0 CPT=1 CNG=0 DTV=0 DTV=1 ATV=0 ATV=1 BSY=1 SD=0 SD=1 Interrupt Source Summary STATUS Set by (new) RDY=1 CIA=1 CD=1 CD=0 CPT=1 CPT=0 CNG=1 DTV=1 DTV=0 ATV=1 ATV=0 BSY=0 SD=1 SD=0 Command completed New Caller ID byte available Carrier detected Carrier lost Call progress tone detected Call progress tone lost Fax calling tone detected DTMF tone detected DTMF tone lost Alert tone detected Alert tone lost File command completed Speech activity detected Speech activity lost Reset by Command issued CIDCTL0 read Carrier lost Carrier detected CPT lost CPT detected CNG lost DTMF tone lost DTMF tone detected Alert tone lost Alert tone detected New command issued Speech activity lost Speech activity detected
An interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. The interrupt is cleared when the host reads the STATUS register. If a new event occurs while the host reads the status register, the status register is updated after the current access is terminated and a new interrupt is generated immediately after the access has ended.
Note: If the internal interrupt occurs after the controller has already selected the device but not yet read the STATUS word, then the STATUS word is updated and the internal interrupt is cleared. Therefore the controller should always evaluate the STATUS word when read.
2.3.5 Abort
If the PSB 4860 cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. After that it sets the ABT bit of the STATUS register and generates an interrupt. The PSB 4860 discards all commands with the exception of a write command to the revision register while ABT is set. Only after the write command to the revision register (with any value) the ABT bit is reset and a reinitialization can take place.
Semiconductor Group
81
10.97
PSB 4860
Functional Description 2.3.6 Revision Register
The PSB 4860 contains a revision register. This register is read only and does not influence operation in any way. A write to the revision register clears the ABT bit of the STATUS register but does not alter the content of the revision register. 2.3.7 Hardware Configuration
The PSB 4860 can be adapted to various external hardware configurations by four special registers: HWCONFIG0 to HWCONFIG3. These registers are usually only written once during initialization and must not be changed while the PSB 4860 is in active mode. It is mandatory that the programmed configuration reflects the external hardware for proper operation. Special care must be taken to avoid I/O conflicts or excess current by enabling inputs without an external driving source. Table 65 can be used as a checklist. Table 65 Register HWCONFIG0 HWCONFIG0 HWCONFIG0 HWCONFIG1 HWCONFIG1 2.3.8 Hardware Configuration Checklist Name OSC ACS MFS ACT Value 1 1 1 1 Check FRDY must not float OSC1/2 must be connected to a crystal CLK must not float (tie low if no clock present) FSC must not float (tie low if no clock present) FSC must not float (tie low if no clock present) PFRDY 1
Frame Synchronization
The PSB 4860 locks itself to either an externally supplied clock or frame sync signal or generates the frame sync signal itself. This internal reference frame sync signal is called master frame sync (MFSC). In addition, the PSB 4860 can derive the AFECLK and AFEFSC from either the main oscillator or an auxiliary clock input. Table 66 shows how AFECLK and MFSC are derived by the PSB 4860. The bits ACS and MFS are contained in the hardware configuration registers. Table 66 ACS 0 0 1 1 0 1 0 1 Frame Synchronization Selection MFS AFECLK XTAL CLK CLK MFSC AFEFSC FSC AFEFSC FSC Application Analog featurephone ISDN stand-alone DECT unused
Semiconductor Group
82
10.97
PSB 4860
Functional Description 2.3.9 Clock Tracking
The PSB 4860 can adjust AFECLK and AFEFSC dynamically to a slightly varying FSC if AFECLK and AFEFSC are derived from the main oscillator (XTAL). This mode requires that both AFEFSC and FSC are nominally running at the same frequency (8 kHz). This feature is especially useful when the FSC signal is not derived from the same clock source as AFECLK (ISDN application). 2.3.10 Dependencies of Modules
There are some restrictions concerning the modules that can be enabled at the same time (table 67). A checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. Table 67 Dependencies of Modules Speech Encoder Speech Enc. Speech Dec. Line EC (24 ms) Acoustic EC DTMF Det. File Cmd.
1)
Speech Decoder X
Line EC (24 ms) X X1)
Acoustic DTMF File EC Detector Command X X X X X B,O B,I B,O,I B,O,I B,O B,O B,I
X X X B,O,I X1) X B,O,I
X B,O
if Speech Decoder is running at slow speed
There are three classes of file commands denoted by the letters B, O and I. Table 68 shows the definition of these classes: Table 68 B O I File Command Classes
Class Description Background commands (Activate, Recompress, Garbage Collection, Initialize) Open Commands (Open, Open Next Free File) Any command executed with EIE=1 (i.e. immediate execution)
Examples: * The line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder is running at slow speed. * If the DTMF detector is running, none of the background file commands (B) must be executed. In addition, no file command must be executed with immediate execution
Semiconductor Group 83 10.97
PSB 4860
Functional Description enabled (I). However, files my be opened and other commands (like read or write) may be executed without immediate execution enabled. Furthermore it may be necessary to restrict the length of the FIR filter of the echo cancellation unit if several other units are operating at the same time. The sum of all weights (table 69) of the simultaneously enabled modules must not exceed 100 at any given time. Table 69 Module Equalizer CPT Detector Caller ID Decoder1) CNG Detector DTMF Generator Echo Cancellation Echo Cancellation Echo Cancellation Echo Cancellation Line Echo Cancellation Universal Attenuator Digital Interface Digital Interface Analog Interface Clock Tracking Miscellaneous
1)
Module Weights Weight Comment 2.8 5.6 4.2 2.6 2.2 52.1 62.5 72.9 83.3 12.7 0.2 1.7 1.7 2.5 0.6 8.0 always active X channel 1 or SSDI channel 2 X X X X X 127 taps (16 ms) 255 taps (32 ms) 383 taps (48 ms) 511 taps (64 ms) X X X X X Example 1 X Example 2 X
The alert tone detector would add another 2.6, but can be disabled after the alert tone has been detected. Therefore it can be left out of the calculation.
Example: * For an analog phone echo cancellation, DTMF tone generation, caller ID reception, and line echo cancellation are necessary. The system uses the PSB 4851 and the equalizer to linearize the loudspeaker. In this case the sum of all weights without echo cancellation is 35.6. Therefore 255 taps can be used for a total of 98.1. * In an ISDN phone echo cancellation, channel 1 of the digital interface, the analog interface with clock tracking and the equalizer shall be enabled at the same time. In
Semiconductor Group
84
10.97
PSB 4860
Functional Description this application the sum of all weights without echo cancellation is 15.6. Therefore 511 taps can be used for a total of 98.9.
Semiconductor Group
85
10.97
PSB 4860
Functional Description 2.4
Interfaces Interfaces
Interfaces
This section describes the interfaces of the PSB 4860. The PSB 4860 supports both an IOM(R)-2 interface with single and double clock mode and a strobed serial data interface (SSDI). However, these two interfaces cannot be used simultaneously as they share some pins. Both interfaces are for data transfer only and cannot be used for programming the PSB 4860. Table 70 lists the features of the two alternative interfaces. Table 70 Signals Channels (bidirectional) Code SSDI vs. IOM(R)-2 Interface IOM(R)-2 4 2 linear PCM, A-law, -law 6 1 linear PCM by signal (DXST, DRST) SSDI
Synchronization within frame by timeslot (programmable) 2.4.1 IOM(R)-2 Interface
The data stream is partitioned into packets called frames. Each frame is divided into a fixed number of timeslots. Each timeslot is used to transfer 8 bits. Figure 41 shows a commonly used terminal mode (three channels ch0, ch1 and ch2 with four timeslots each). The first timeslot (in figure 41: B1) is denoted by number 0, the second one (B2) by 1 and so on. 125 s
FSC
DD/DU
B1
B2 ch0
M0
CI0
IC1
IC2 ch1
M1
CI1 ch2
Figure 41 IOM(R)-2 Interface - Frame Structure The signal FSC is used to indicate the start of a frame. Figure 42 shows as an example two valid FSC-signals (FSC, FSC*) which both indicate the same clock cycle as the first clock cycle of a new frame (T1).
Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However, programming is not supported via the monitor channels.
Semiconductor Group 86 10.97
PSB 4860
Functional Description
T1 DCL
T2
FSC
FSC*
Figure 42 IOM(R)-2 Interface - Frame Start The PSB 4860 supports both single clock mode and double clock mode. In single clock mode, the bit rate is equal to the clock rate. Bits are shifted out with the rising edge of DCL and sampled at the falling edge. In double clock mode, the clock runs at twice the bit rate. Therefore for each bit there are two clock cycles. Bits are shifted out with the rising edge of the first clock cycle and sampled with the falling edge of the second clock cycle. Figure 43 shows the timing for single clock mode and figure 44 shows the timing for double clock mode.
T1 DCL
T2
DU/DX
bit 0
bit 1
bit 2
DD/DR
bit 0
bit 1
bit 2
Figure 43 IOM(R)-2 Interface - Single Clock Mode
Semiconductor Group
87
10.97
PSB 4860
Functional Description
T1 DCL
T2
T3
T4
T5
DU/DX
bit 0
bit 1
bit 2
DD/DR
bit 0
bit 1
Figure 44 IOM(R)-2 Interface - Double Clock Mode The PSB 4860 supports up to two channels simultaneously for data transfer. Both the coding (PCM or linear) and the data direction (DD/DU assignment for transmit/receive) can be programmed individually for each channel. Table 71 shows the registers used for configuration of the IOM(R)-2 interface. Table 71 IOM(R)-2 Interface Registers Name EN DCL NTS EN TS DD PCM PCD EN TS DD PCM PCD Comment Interface enable Selection of clock mode Number of timeslots within frame Channel 1 enable First timeslot (channel 1) Data Direction (channel 1) 8 bit code or 16 bit linear PCM (channel 1) 8 bit code (A-law or -law, channel 1) Channel 2 enable First timeslot (channel 2) Data Direction (channel 2) 8 bit code or 16 bit linear PCM (channel 2) 8 bit code (A-law or -law, channel 2)
Register # of Bits SDCONF 1 SDCONF 1 SDCONF 6 SDCHN1 1 SDCHN1 6 SDCHN1 1 SDCHN1 1 SDCHN1 1 SDCHN2 1 SDCHN2 6 SDCHN2 1 SDCHN2 1 SDCHN2 1
In A-law or -law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. In linear mode, 16 bits are needed for a single channel. In this mode, two consecutive timeslots are used for data transfer. Bits 8 to 15 are transferred
Semiconductor Group
88
10.97
PSB 4860
Functional Description within the first timeslot and bits 0 to 7 are transferred within the next timeslot. The first timeslot must have an even number. The most significant bit is always transmitted first.
Semiconductor Group
89
10.97
PSB 4860
Functional Description 2.4.2 SSDI Interface
The SSDI interface is intended for seamless connection to low-cost burst mode controllers (e.g. PMB 27251) and supports a single channel in each direction. The data stream is partitioned into frames. Within each frame one 16 bit value can be sent and received by the PSB 4860. The start of a frame is indicated by the rising edge of FSC. Data is always sampled at the falling edge of DCL and shifted out with the rising edge of DCL. The SSDI transmitter and receiver are operating independently of each other except that both use the same FSC and DCL signal. 2.4.2.1 SSDI Interface - Transmitter
The PSB 4860 indicates outgoing data (on signal DX) by activating DXST for 16 clocks. The signal DXST is activated with the same rising edge of DCL that is used to send the first bit (Bit 15) of the data. DXST is deactivated with the first rising edge of DCL after the last bit has been transferred. The PSB 4860 drives the signal DX only when DXST is activated. Figure 45 shows the timing for the transmitter. 125 s
FSC
DXST
DCL
DU/DX
bit 15
bit 14
bit 1
bit 0
Figure 45 SSDI Interface - Transmitter Timing 2.4.2.2 SSDI Interface - Receiver
Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly 16 DCL clocks. As there may be more than one DRST pulses within a single frame the PSB 4860 can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In order to detect the first pulse properly, DRST must not be active at the rising edge of FSC. In figure 46 the PSB 4860 is listening to the third DRST pulse (n=3).
Semiconductor Group
90
10.97
PSB 4860
Functional Description
FSC
DRST active pulse (n=3)
Figure 46 SSDI Interface - Active Pulse Selection Figure 47 shows the timing for the SSDI receiver. 125 s
FSC
DRST
DCL
DD/DR
bit 15
bit 14
bit 1
bit 0
Figure 47 SSDI Interface - Receiver Timing Table 72 shows the registers used for configuration of the SSDI interface. Table 72 SSDI Interface Register Name NAS Comment Number of active DRST strobe
Register # of Bits SDCHN1 4
Semiconductor Group
91
10.97
PSB 4860
Functional Description 2.4.3 Analog Front End Interface
The PSB 4860 uses a four wire interface similar to the IOM(R)-2 interface to exchange information with the analog front end (PSB 4851). The main difference is that all timeslots and the channel assignments are fixed as shown in figure 48.
.
125 s
AFEFS AFEDD AFEDU
Channel C1 16 bit
Channel C2 16 bit
Channel C3 8 bit
unused
0
0
0
OV
ALS
Figure 48 Analog Front End Interface - Frame Structure Voice data is transferred in 16 bit linear coding in two bidirectional channels C1 and C2. An auxiliary channel C3 is used to transfer the current setting of the loudspeaker amplifier ALS to the PSB 4860. The remaining bits are fixed to zero. In the other direction C3 transfers an override value for ALS from the PSB 4860 to the PSB 4851. An additional override bit OV determines if the currently transmitted value should override the AOAR:LSC1) setting. The AOAR:LSC setting is not affected by C3:ALS override. Table 73 shows the source control of the gain for the ALS amplifier. Table 73 0 1 1 Control of ALS Amplifier C3:OV 0 1 Gain of ALS amplifier AOAR:LSC AOAR:LSC C3:ALS AOPR:OVRE
Furthermore the AFE interface can be enabled or disabled according to table 74. Table 74 Register AFECTL Analog Front End Interface Register # of Bits 1 Name EN Comment Interface enable
1)
See specification of PSB 4851, automatically set by the PSB 4860 in loudhearing mode.
Semiconductor Group
92
10.97
PSB 4860
Functional Description
T1 AFECLK
T2
AFEFS
Figure 49 Analog Front End Interface - Frame Start Figure 49 shows the synchronization of a frame by AFEFS. The first clock of a new frame (T1) is indicated by AFEFS switching from low to high before the falling edge of T1. AFEFS may remain high during subsequent cycles up to T32.
T1 AFECLK
T2
AFEDU
bit 0
bit 1
bit 2
AFEDD
bit 0
bit 1
bit 2
Figure 50 Analog Front End Interface - Data Transfer The data is shifted out with the rising edge of AFECLK and sampled at the falling edge of AFECLK (figure 50). If AOPR:OVRE is not set, the channel C3 is not used by the PSB 4851. All values (C1, C2, C3:ALS) are transferred MSB first. The data clock (AFECLK) rate is fixed at 6.912 MHz. Table 75 shows the clock cycles used for the three channels. Table 75Analog Front End Interface Clock Cycles Clock Cycles T1-T16 T17-T32 T33-T40 T41-T864 AFEDD (driven by PSB 4860) C1 data C2 data C3 data 0 AFEDU (driven by PSB 4851) C1 data C2 data C3 data tristate
Semiconductor Group
93
10.97
PSB 4860
Functional Description 2.4.4 Serial Control Interface
The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled by the PSB 4860 at the rising edge of SCLK and shifted out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. The accesses to the PSB 4860 can be divided into three classes: 1. Configuration Read/Write 2. Status/Data Read 3. Register Read/Write If the PSB 4860 is in power down mode, a read access to the status register does not deliver valid data with the exception of the RDY bit. After the status has been read the access can be either terminated or extended to read data from the PSB 4860. A register read/write access can only be performed when the PSB 4860 is ready. The RDY bit in the status register provides this information. Any access to the PSB 4860 starts with the transfer of 16 bits to the PSB 4860 over line SDR. This first word specifies the access class, access type (read or write) and, if necessary, the register accessed. If a configuration register is written, the first word also includes the data and the access is terminated. Likewise, if a register read is issued, the access is terminated after the first word. All other accesses continue by the transfer of the status register from the PSB 4860 over line SDX. If a register (excluding configuration) is to be written, the next 16 bits containing the data are transferred over line SDR and the access is terminated. Figures 51 to 54 show the timing diagrams for the different access classes and types to the PSB 4860.
CS
SCLK
SDR
c15 c14
c1
c0
SDX
s15 s14
s1
s0
INT c15,..,c0: command word for status register read : s15,..,s0: status register:
Figure 51 Status Register Read Access
Semiconductor Group
94
10.97
PSB 4860
Functional Description
CS
SCLK
SDR
c15 c14
c1
c0
SDX
s15 s14
s1
s0 d15 d14
d1
d0
c15,..,c0: command word for data read: s15,..,s0: status register: d15,..,d0: data to be read:
Figure 52 Data Read Access
CS
SCLK
SDR
c15 c14
c1
c0
d15 d14
d1
d0
SDX
s15 s14
s1
s0
c15,..,c0: command word for register write: s15,..,s0: status register: d15,..,d0: data to be written :
Figure 53 Register Write Access
Semiconductor Group
95
10.97
PSB 4860
Functional Description
CS
SCLK
SDR
c15 c14
c1
c0
SDX
s15 s14
s1
s0 d15 d14
d1
d0
c15,..,c0: command word for configuration register read: s15,..,s0: status register : d15,..,d0: data to be read:
Figure 54 Configuration Register Read Access Configuration registers at even adresses use bit positions d 7-d0 while configuration registers at odd adresses use bit positions d15-d8.
CS
SCLK
SDR
c15 c14
c1
c0
c15,..,c0: command word for configuration register write: or register read:
Figure 55 Configuration Register Write Access or Register Read Command The internal interrupt signal is cleared when the first bit of the status register is put on SDX. However, externally the signal INT is deactivated as long as CS stays low. If the internal interrupt signal is not cleared or another event causing an interrupt occurs while the microcontroller is already reading the status belonging to the first event then INT goes low again immediately after CS is removed. The timing is shown in figure 51. Table 76 shows the formats of the different command words. All other command words are reserved.
Semiconductor Group
96
10.97
PSB 4860
Functional Description Table 76 Command Words for Register Access
15 Read Status Register or Data Read Access Read Register Write Register Read Configuration Reg. Write Configuration Reg. 0 0 0 0 0 14 0 1 1 1 1 13 1 0 0 1 1 12 1 1 0 1 0 0 0 0 0 R W 0 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
REG REG 0 0 0 0 0 0 0
DATA
In case of a configuration register write, W determines which configuration register is to be written (table 77): Table 77 9 0 0 1 1 8 0 1 0 1 Address Field W for Configuration Register Write Register HWCONFIG 0 HWCONFIG 1 HWCONFIG 2 HWCONFIG 3
In case of a configuration register read, R determines which pair of configuration registers is to be read (table 78): Table 78 9 0 1 Address Field R for Configuration Register Read
Register pair HWCONFIG 0 / HWCONFIG 1 HWCONFIG 2 / HWCONFIG 3
Note: Reading any register except the status register or a hardware configuration register requires at least two accesses. The first access is a register read command (figure 55). With this access the register address is transferred to the. After that access data read accesses (figure 52) must be executed. The first data read access with STATUS:RDY=1 delivers the value of the register.
Semiconductor Group
97
10.97
PSB 4860
Functional Description 2.4.5 Memory Interface
The PSB 4860 supports either Flash Memory or ARAM/DRAM as external memory for storing messages. If ARAM/DRAM is used, an EPROM can be added optionally to support read-only messages (e.g. voice prompts). Table 79 summarizes the different configurations supported. Table 79 Mbit 1 2 4 4 8 16 16 32 32 64 64 128 4-128 16-128 Supported Memory Configurations Type ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM FLASH FLASH 16Mx4 16Mx4 8Mx8 16Mx4 512kx8 devices 2Mx8 devices 4Mx4 2x2Mx8 1Mx4 4Mx4 2Mx8 4Mx4 Bank 0 (D0-D3) 256kx4 256kx4 1Mx4 512kx8 1Mx4 2k or 4k refresh 2k refresh 2k or 4k refresh 2k refresh 4k or 8k refresh 4k or 8k refresh 4k or 8k refresh KM29N040 KM29N16000 Bank 1 (D4-D7) 256kx4 Comment
If ARAM/DRAM is used, the total amount of memory must be a power of two and all devices must be of the same type. The pin FRDY must be tied high. For flash devices, the PSB 4860 supports in-circuit programming of voice prompts by releasing the control lines during reset and (optionally) power down. Instead of actively driving the lines FCS, FOE, FWE, FCLE and ALE these lines are pulled high by a weak pullup during reset and (optionally) power down.
Semiconductor Group
98
10.97
PSB 4860
Functional Description 2.4.5.1 ARAM/DRAM Interface
The PSB 4860 supports up to two banks of memory which may be 4 bit or 8 bit wide (Figure 56). If both banks are used they must be populated identically.
MA0-MA15 MD0-MD3 RAS CAS0 W
A0-A12 D0-D3 RAS CAS W OE
MA0-MA15 MD0-MD7 RAS CAS0 W
A0-A12 D0-D7 RAS CAS W OE
PSB 4860
PSB 4860
single 4 bit bank
single 8 bit bank
MA0-MA15 MD0-MD3 RAS CAS0 W
A0-A12 D0-D3 RAS CAS W OE
MA0-MA15 MD0-MD7 RAS CAS0 W
A0-A12 D0-D7 RAS CAS W OE
PSB 4860
PSB 4860
A0-A12 MD4-MD7 D0-D3 RAS CAS1 CAS W OE CAS1
A0-A12 D0-D7 RAS CAS W OE
two 4 bit banks
two 8 bit banks
Figure 56 ARAM/DRAM Interface - Connection Diagram
Semiconductor Group
99
10.97
PSB 4860
Functional Description The PSB 4860 also supports different internal organizations of ARAM/DRAM chips. Table 80 shows the necessary connections on the address bus. Table 80 256k x4 512k x8 1M x4 4M x4 (2k refresh) 4M x4 (4k refresh) 2M x8 16M x4 (4k refresh) 16M x4 (8k refresh) 8M x8 (4k refresh) 8M x8 (8k refresh)
1)
Address Line Usage (ARAM/DRAM Mode) CS91) MA0-MA8 MA9 1 1 0 0 0 0 0 0 0 0 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A10 A10 A10 A10 A10 A10 A10 A11 A11 A11 A11 A12 A12 A11 MA10 MA11 MA12 MA13
ARAM/DRAM
see chip control register CCTL
The timing of the ARAM/DRAM interface is shown in figures 57 to 59. The timing is derived form the internal memory clock MCLK* which runs at a quarter of the system clock.
MCLK* MA0-MA13 RAS CAS0,CAS1 MD0-MD7 Figure 57 ARAM/DRAM Interface - Read Cycle Timing
row addr. col. addr.
Semiconductor Group
100
10.97
PSB 4860
Functional Description
MCLK* MA0-MA13 RAS CAS0,CAS1 W MD0-MD7
data out row addr. col. addr.
Figure 58 ARAM/DRAM Interface - Write Cycle Timing
MCLK* RAS CAS0,CAS1 Figure 59 ARAM/DRAM Interface - Refresh Cycle Timing The PSB 4860 ensures that RAS remains inactive for at least one MCLK*-cycle between successive accesses. The frequency at which refresh cycles are performed is shown in table 81. Table 81 64 kHz
1)
Refresh Frequency Selection Comment Memory access (e.g. recording) in progress
Refresh frequency
8, 16, 32 or 64 kHz1) No memory access in progress or power-down
as programmed by HWCONFIG2:RSEL
Semiconductor Group
101
10.97
PSB 4860
Functional Description 2.4.5.2 EPROM Interface
The PSB 4860 supports an EPROM in parallel with ARAM/DRAM. This interface is always 8 Bits wide and supports a maximum of 256 kB. Figure 60 shows a connection diagram and figure 61 the timing. This interface supports read cycles only.
SPS1 SPS0 MA0-MA15 MD0-MD7 VPRD
A17 A16 A0-A15 D0-D7 CE OE
PSB 4860
Figure 60 EPROM Interface - Connection Diagram
MCLK* MA0-MA15 VPRD MD0-MD7 Figure 61 EPROM Interface - Read Cycle Timing
Note: In order to access more than 64 kB the pins SPS0 and SPS1 can be programmed to provide the address lines A16 and A17. In this mode A16 and A17 remain stable during the whole read cycle. See the register SPSCTL for programming information.
Semiconductor Group
102
10.97
PSB 4860
Functional Description 2.4.5.3 Flash Memory Interface
The PSB 4860 has special support for the KM29N040 and KM29N16000 or equivalent devices. No external components are required for up to four KM29N040. Figure 62 shows the connection diagram for a single device.
MD0-MD7 ALE FCS FOE FWR FCLE FRDY
D0-D7 ALE CE RE WE CLE R/B +5V WP
PSB 4860
Figure 62 Flash Memory Interface - Connection Diagram Table 82 shows the signals output during a device access on the MA-lines. The address bits can used by an external decoder. Up to four KM29N040 are supported directly by the decoded select signals FCS0-FCS3. Table 82 MA11 FCS3 Address Line Usage (Samsung Mode) MA10 FCS2 MA9 FCS1 MA8 FCS0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 A23 A22 A21 A20 A19 A18 A17 A16
Semiconductor Group
103
10.97
PSB 4860
Functional Description Figure 63 shows an application with three KM29N040 devices.
WP D0-D7 CE RE WE R/B CLE ALE MD0-MD7 FOE FWR FRDY FCLE ALE MA8 MA9 MA10 D0-D7 CE RE WE R/B CLE ALE
WP D0-D7 CE RE WE R/B CLE ALE
PSB 4860
WP
+5V
Figure 63 Flash Memory Interface - Multiple Devices An access to the Flash Memory can consist of several partial access cycles where only the timing of the partial access cycles is defined but not the time between two adjacent partial access cycles. The PSB 4860 performs three types of partial access cycles: 1. Command write 2. Address write 3. Data read/write Table 83 shows the supported accesses and the corresponding partial access cycles. Table 83 Flash Memory Command Summary Command Address Address Address # of Data Command write write 1 write 2 write 3 read/write write FF 70 60 00 80 A8-A15 A0-A7 A0-A7 A16-A23 A8-A15 A8-A15 A16-A23 A16-A23 1 1-32 1-32 D0 10
Access RESET STATUS READ BLOCK ERASE READ WRITE
Semiconductor Group
104
10.97
PSB 4860
Functional Description The timing for the partial access cycles is shown in figures 64 to 65. Note that both FCS and MA0-MA15 remain stable between the first and the last partial access of a device access.
MCLK* MA0-MA11 FCS FWR FCLE MD0-MD7
data out
Figure 64 Flash Memory Interface - Command Write
t0
t1
t2
t3
MCLK* FWR ALE MD0-MD7
data out
address latch cycle
Figure 65 Flash Memory Interface - Address Write As there is no access that starts or stops with an address write cycle (figure 65) FCS is already low at the start of this cycle and also remains low.
Semiconductor Group
105
10.97
PSB 4860
Functional Description
t0
t1
t2
t3
MCLK* FWR MD0-MD7
data out
write cycle
Figure 66 Flash Memory Interface - Data Write As there is no access that starts or stops with a data write cycle (figure 66) FCS is already low at the start of this cycle and also remains low.
t0
t1
t2
t3
MCLK* FOE MD0-MD7
data in
read cycle
Figure 67 Flash Memory Interface - Data Read If the device access ends with a read cycle, the FCS-signals go inactive after t3 of the last read cycle. The data is latched at the rising edge of FOE.
Semiconductor Group
106
10.97
PSB 4860
Functional Description 2.4.6 Auxiliary Parallel Port
The PSB 4860 provides an auxiliary parallel port if the memory interface is in Samsung mode and only one device is used. In this case the lines MA0 to MA15 are not needed for the memory interface and can therefore be used for an auxiliary parallel port. This port has two modes: static mode and multiplex mode. 2.4.6.1 Static Mode
In static mode all pins of the auxiliary parallel port interface have identical functionality. Any pin can be configured as an output or an input. Pins configured as outputs provide a static signal as programmed by the controller. Pins configured as inputs are monitoring the signal continuously without latching. The controller always reads the current value. Table 84 shows the registers used for static mode. Table 84 DOUT3 DIN DDIR 2.4.6.2 Static Mode Registers 16 16 16 Output signals (for pins configured as outputs) Input signals (for pins configured as inputs) Pin direction
Register # of bits Comment
Multiplex Mode
In multiplex mode, the PSB 4860 uses MA12-MA15 to distinguish four timeslots. Each timeslot has a duration of approximately 2 ms. The timeslots are separated by a gap of approximately 125 s in which none of the signals at MA12-MA15 are active. The PSB 4860 multiplexes three more output registers to MA0-MA11 in timeslots 0, 1 and 2. In timeslot 3 the direction of the pins can be programmed. For input pins, the signal is latched at the falling edge of MA15. Table 85 shows the registers used for multiplex mode. This mode is useful for scanning keys or controlling seven segment LED displays. Table 85 DOUT0 DOUT1 DOUT2 DOUT3 DIN DDIR Multiplex Mode Registers 12 12 12 12 12 12 Output signals on MA0-MA11 while MA15=1 Output signals on MA0-MA11 while MA14=1 Output signals on MA0-MA11 while MA13=1 Output signals (for pins configured as outputs) while MA12=1 Input signals (for pins configured as inputs) at falling edge of MA12 Pin direction during MA12=1
107 10.97
Register # of bits Comment
Semiconductor Group
PSB 4860
Functional Description Figure 68 shows the timing diagram for multiplex mode.
2 ms MA15
MA14
MA13
MA12
MA0-MA11
DOUT0
DOUT1
DOUT2
DIN/DOUT3
DOUT0
Figure 68 Auxiliary Parallel Port - Multiplex Mode
Note: In either mode the voltage at any pin (MA0 to MA15) must not exceed VDD.
Semiconductor Group
108
10.97
PSB 4860
Detailed Register Description 3 Detailed Register Description
The PSB 4860 has a single status register (read only) and an array of data registers (read/write). The purpose of the status register is to inform the external microcontroller of important status changes of the PSB 4860 and to provide a handshake mechanism for data register reading or writing. If the PSB 4860 generates an interrupt, the status register contains the reason of the interrupt. 3.1 15
RDY
1)
Status Register 0
ABT 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV -1) -1) -1)
undefined
RDY
Ready 0: The last command (if any) is still in progress. 1: The last command has been executed.
ABT
Abort 0: No exception during operation 1: Some exception other than reset caused the PSB 4860 to abort any operation currently in progress. The external microcontroller should reinitialize the PSB 4860 to ensure proper operation. The ABT bit is cleared by writing any value to register REV. No other command is accepted by the PSB 4860 while ABT is set.
CIA
Caller ID Available 0: No new data for caller ID 1: New caller ID byte available
CD
Carrier Detect 0: No carrier detected 1: Carrier detected
Semiconductor Group
109
10.97
PSB 4860
Detailed Register Description CPT Call Progress Tone 0: Currently no call progress tone detected or pause detected (raw mode) 1: Currently a call progress is detected CNG Fax Calling Tone 0: Currently no fax calling tone detected 1: Currently a fax calling tone is detected SD Speech Detected 0: No speech detected 1: Speech signal at input of coder ERR Error (File Command) 0: No error 1: Last file command resulted in an error BSY Busy (File Command) 0: File system idle 1: File system still busy (also set during encoding/decoding) DTV DTMF Tone Valid 0: No new DTMF code available 1: New DTMF code available in DDCTL ATV Alert Tone Valid 0: No new alert tone code available 1: New alert tone code available in ADCTL0
Semiconductor Group
110
10.97
PSB 4860
Detailed Register Description 3.2 Hardware Configuration Registers
HWCONFIG 0 - Hardware Configuration Register 0 7
PD ACS RTC OSC PPSDI PFRDY PPINT
0
PPSDX
PPSDX Push/Pull for SDX 0: The SDX pin has open-drain characteristic 1: The SDX pin has push/pull characteristic PPINT Push/Pull for INT 0: The INT pin has open-drain characteristic 1: The INT pin has push/pull characteristic PFRDY Pullup for FRDY 0: The internal pullup resistor of pin FRDY is enabled 1: The internal pullup resistor of FRDY is disabled PPSDI Push/Pull for SDI interface 0: The DU and DD pins have open-drain characteristic 1: The DU and DD pins have push/pull characteristic OSC Enable Auxiliary Oscillator 0: The auxiliary oscillator (OSC1, OSC2) is disabled 1: The auxiliary oscillator (OSC1, OSC2) is enabled RTC Enable Real Time Clock 0: The real time clock is disabled 1: The real time clock (RTC) is enabled. ACS AFE Clock Source 0: AFECLK is derived from the main oscillator 1: AFECLK is derived from the CLK input PD Power Down (read only) 0: The PSB 4860 is in active mode 1: The PSB 4860 is in power down mode
Semiconductor Group 111 10.97
PSB 4860
Detailed Register Description HWCONFIG 1 - Hardware Configuration Register 1 7
APP ACT ADS MFS XTAL
0
SSDI
APP
Auxiliary Parallel Port
7 0 0 1 1 6 0 1 0 1 Description normal (ARAM/DRAM, Intel type flash, voice prompt EPROM) APP static mode APP multiplex mode reserved
ACT
AFE Clock Tracking 0: AFECLK tracking disabled 1: AFECLK tracking enabled
ADS
AFE Double Speed 0: 8 kHz AFEFSC 1: 16 kHz AFEFSC
MFS
Master Frame Sync Selection 0: AFEFSC 1: FSC
XTAL
XTAL Frequency
2 0 0 1 1
1)
1 0 1 0 1
Factor p1) reserved 4.5 reserved reserved
Description reserved 31.104 MHz reserved reserved
The factor p is needed to calculate the clock frequency at AFECLK.
SSDI
SSDI Interface Selection 0: IOM(R)-2 Interface 1: SSDI Interface
Semiconductor Group
112
10.97
PSB 4860
Detailed Register Description HWCONFIG 2 - Hardware Configuration Register 2 7
PPM ESDX ESDR CSEL CHS RSEL
0
PPM
Push/Pull for Memory Interface (reset, power down) 0: The signals for the memory interface have push/pull characteristic 1: The signals for the memory interface have pullup/pulldown characteristic
ESDX
Edge Select for DX 0: DX is transmitted with the rising edge of DCL 1: DX is transmitted with the falling edge of DCL
ESDR
Edge Select for DR 0: DR is latched with the falling edge of DCL 1: DR is latched with the rising edge of DCL
CSEL
Codec Selection for AFE interface 0: Interface to PSB 4851 1: Interface to AK 4510
CHS
Channel Select (AK 4510 only)
3 0 0 1 1 2 0 1 0 1 Description left channel of AK 4510 right channel of AK4510 left and right channel reserved
RSEL
Refresh Select
1 0 0 1 1 0 0 1 0 1 Description 64 kHz refresh frequency 32 kHz refresh frequency 16 kHz refresh frequency 8 kHz refresh frequency
Semiconductor Group
113
10.97
PSB 4860
Detailed Register Description HWCONFIG 3 - Hardware Configuration Register 3 7
0 0 0 0 0 0 0
0
0
Semiconductor Group
114
10.97
PSB 4860
Detailed Register Description 3.3 Read/Write Registers
The following sections contains all read/write registers of the PSB 4860. The register addresses are given as hexadecimal values. Registers marked with an R are affected by reset or a wake up after power down. All other registers retain their previous value. No access must be made to addresses other than those associated with a read/write register. 3.3.1 00h 01h R 02h R 03h R 04h R 05h R 06h R 07h R 08h R 09h R 0Ah R 0Bh R 0ChR 0DhR 0Eh R 0Fh R 10h R 11h R 12h 13h 14h 15h 16h R 17h 18h 19h 1Ah R 1Bh 1ChR 1Dh 20h R 21h 22h Register Table Long Name Page REV CCTL INTM AFECTL IFS1 IFG1 IFG2 IFS2 IFG3 IFG4 SDCONF SDCHN1 IFS3 SDCHN2 IFS4 IFG5 UA DGCTL DGF1 DGF2 DGL DGATT CNGCTL CNGBT CNGLEV CNGRES ATDCTL0 ATDCTL1 CIDCTL0 CIDCTL1 CPTCTL CPTTR CPTMN Revision.............................................................................. 119 Chip Control ....................................................................... 120 Interrupt Mask Register ...................................................... 121 Analog Front End Interface Control.................................... 122 Interface Select 1 ............................................................... 123 Interface Gain 1.................................................................. 124 Interface Gain 2.................................................................. 125 Interface Select 2 ............................................................... 126 Interface Gain 3.................................................................. 127 Interface Gain 4.................................................................. 128 Serial Data Interface Configuration .................................... 129 Serial Data Interface Channel 1 ......................................... 130 Interface Select 3 ............................................................... 132 Serial Data Interface Channel 2 ......................................... 133 Interface Select 4 ............................................................... 134 Interface Gain 5.................................................................. 135 Universal Attenuator........................................................... 136 DTMF Generator Control.................................................... 137 DTMF Generator Frequency 1 ........................................... 138 DTMF Generator Frequency 2 ........................................... 139 DTMF Generator Level....................................................... 140 DTMF Generator Attenuation ............................................. 141 Calling Tone Control........................................................... 142 CNG Burst Time ................................................................. 143 CNG Minimal Signal Level ................................................. 144 CNG Signal Resolution ...................................................... 145 Alert Tone Detection 0........................................................ 146 Alert Tone Detection 1........................................................ 147 Caller ID Control 0.............................................................. 148 Caller ID Control 1.............................................................. 149 Call Progress Tone Control ................................................ 150 Call Progress Tone Thresholds.......................................... 151 CPT Minimum Times.......................................................... 152
115 10.97
Address. Name
Semiconductor Group
PSB 4860
Detailed Register Description 23h 24h 25h R 26h 27h 28h 29h R 2Ah 2Bh 2Eh R 2Fh 30h R 31h 32h 34h R 38h R 39h R 3Ah 3Bh 3Ch 3Dh 3Eh 40h R 41h R 42h R 43h R 47h R 48h R 49h R 4Ah R 4Bh R 4ChR 4DhR 4Eh 4Fh R 60h R 62h R 63h R 64h 65h 66h 67h 68h CPTMX CPTDT LECCTL LECLEV LECATT LECMGN DDCTL DDTW DDLEV FCFCTL FCFCOF SCCTL SCCT2 SCCT3 SDCTL AGCCTL AGCATT AGC1 AGC2 AGC3 AGC4 AGC5 FCTL FCMD FDATA FPTR SPSCTL RTC1 RTC2 DOUT0 DOUT1 DOUT2 DOUT3 DIN DDIR SCTL SSRC1 SSRC2 SSDX1 SSDX2 SSDX3 SSDX4 SSDR1 CPT Maximum Times......................................................... 153 CPT Delta Times ................................................................ 154 Line Echo Cancellation Control .......................................... 155 Minimal Signal Level for Line Echo Cancellation ............... 156 Externally Provided Attenuation ......................................... 157 Margin for Double Talk Detection....................................... 158 DTMF Detector Control ...................................................... 159 DTMF Detector Signal Twist .............................................. 160 DTMF Detector Minimum Signal Level............................... 161 Equalizer Control................................................................ 162 Equalizer Coefficient Data.................................................. 164 Speech Coder Control........................................................ 165 Speech Coder Control 2..................................................... 166 Speech Coder Control 3..................................................... 167 Speech Decoder Control .................................................... 168 AGC Control ....................................................................... 169 Automatic Gain Control Attenuation ................................... 170 Automatic Gain Control 1 ................................................... 171 Automatic Gain Control 2 ................................................... 172 Automatic Gain Control 3 ................................................... 173 Automatic Gain Control 4 ................................................... 174 Automatic Gain Control 5 ................................................... 175 File Control ......................................................................... 176 File Command .................................................................... 177 File Data ............................................................................. 179 File Pointer ......................................................................... 180 SPS Control........................................................................ 181 Real Time Clock 1 .............................................................. 182 Real Time Clock 2 .............................................................. 183 Data Out (Timeslot 0) ......................................................... 184 Data Out (Timeslot 1) ......................................................... 185 Data Out (Timeslot 2) ......................................................... 186 Data Out (Timeslot 3 or Static Mode)................................. 187 Data In (Timeslot 3 or Static Mode).................................... 188 Data Direction (Timeslot 3 or Static Mode) ........................ 189 Speakerphone Control ....................................................... 190 Speakerphone Source 1..................................................... 191 Speakerphone Source 2..................................................... 192 Speech Detector (Transmit) 1 ............................................ 193 Speech Detector (Transmit) 2 ............................................ 194 Speech Detector (Transmit) 3 ............................................ 195 Speech Detector (Transmit) 4 ............................................ 196 Speech Detector (Receive) 1 ............................................. 197
116 10.97
Semiconductor Group
PSB 4860
Detailed Register Description 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 80h 81h 82h 83h 84h SSDR2 SSDR3 SSDR4 SSCAS1 SSCAS2 SSCAS3 SSCLS1 SSCLS2 SSCLS3 SATT1 SATT2 SAGX1 SAGX2 SAGX3 SAGX4 SAGX5 SAGR1 SAGR2 SAGR3 SAGR4 SAGR5 SLGA SAELEN SAEATT SAEGS SAEPS1 SAEPS2 Speech Detector (Receive) 2 ............................................. 198 Speech Detector (Receive) 3 ............................................. 199 Speech Detector (Receive) 4 ............................................. 200 Speech Comparator (Acoustic Side) 1 ............................... 201 Speech Comparator (Acoustic Side) 2 ............................... 202 Speech Comparator (Acoustic Side) 3 ............................... 203 Speech Comparator (Line Side) 1...................................... 204 Speech Comparator (Line Side) 2...................................... 205 Speech Comparator (Line Side) 3...................................... 206 Attenuation Unit 1............................................................... 207 Attenuation Unit 2............................................................... 208 Automatic Gain Control (Transmit) 1.................................. 209 Automatic Gain Control (Transmit) 2.................................. 210 Automatic Gain Control (Transmit) 3.................................. 211 Automatic Gain Control (Transmit) 4.................................. 212 Automatic Gain Control (Transmit) 5.................................. 213 Automatic Gain Control (Receive) 1................................... 214 Automatic Gain Control (Receive) 2................................... 215 Automatic Gain Control (Receive) 3................................... 216 Automatic Gain Control (Receive) 4................................... 217 Automatic Gain Control (Receive) 5................................... 218 Line Gain ............................................................................ 219 Acoustic Echo Cancellation Length.................................... 220 Acoustic Echo Cancellation Double Talk Attenuation ........ 221 Acoustic Echo Cancellation Global Scale .......................... 222 Acoustic Echo Cancellation Partial Scale........................... 223 Acoustic Echo Cancellation First Block .............................. 224
Note: Registers CCTL, FCTL, FCMD, FDATA, FPTR, RTC1, RTC2, DOUT0, DOUT1, DOUT2, DOUT3 and DDIR are only affected by reset, not by wakeup. For register SPSCTL see the register description for the exact behaviour.
3.3.2 Register Naming Conventions
Several registers contain one or more fields for input signal selection. All fields labelled I1 (I2, I3) are five bits wide and use the same coding as shown in table 86. Table 86 4 0 0 3 0 0 Signal Encoding 2 0 0 1 0 0 0 0 1 Signal Description S0 S1 Silence Analog line input (channel 1 of PSB 4851 interface)
Semiconductor Group
117
10.97
PSB 4860
Detailed Register Description Table 86 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 Signal Encoding 2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Signal Description S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 Analog line output (channel 1 of PSB 4851 interface) Microphone input (channel 2 of PSB 4851 interface) Loudspeaker/Handset output (channel 2 of PSB 4851 interface) Serial interface input, channel 1 Serial interface output, channel 1 Serial interface input, channel 2 Serial interface output, channel 2 DTMF generator output DTMF generator auxiliary output Speakerphone output (acoustic side) Speakerphone output (line side) Speech decoder output Universal attenuator output Line echo canceller output AGC unit output (after AGC) AGC unit output (before AGC) Equalizer output reserved reserved reserved
Semiconductor Group
118
10.97
PSB 4860
Detailed Register Description 00h 15
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
REV
Revision 0
0
The revision register can only be read. For the PSB 4860, V2.1, all bits except bit 12 are zero.
Note: A write access to the revision register does not alter its content. It does, however, reset the ABT bit of the STATUS register.
Semiconductor Group
119
10.97
PSB 4860
Detailed Register Description 01h R CCTL 15
0 0 0 0 MV 0 0 PD 0 0 0 MQ MT CS9
Chip Control 0
SAS
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MV
Voice Prompt Directory 0: not available 1: available (within EPROM or Flash)
PD
Power Down 0: PSB 4860 is in active mode 1: enter power-down mode
MQ
Memory Quality 0: ARAM 1: DRAM
MT
Memory Type
3 0 1 2 0 1 Description ARAM/DRAM Samsung flash memory
CS9
CAS selection 0: other memory 1: 256kx4 or 512kx8 memory
SAS
Split Address Space 0: other ARAM/DRAM 1: two 2Mx8 devices
Semiconductor Group
120
10.97
PSB 4860
Detailed Register Description 02h R INTM 15
RDY 1 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV 0 0
Interrupt Mask Register 0
0
Reset Value
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
If a bit of this register is reset (set to 0), the corresponding bit of the status register does not generate an interrupt. If a bit is set (set to 1), an external interrupt can be generated by the corresponding bit of the status register.
Semiconductor Group
121
10.97
PSB 4860
Detailed Register Description 03h R AFECTL 15
0 0 0 0 ALS 0 0 0 0 0 0 0
Analog Front End Interface Control 0
EN
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0
ALS
Loudspeaker Amplification
This value is transferred on channel C3 of the AFE interface. If the PSB 4851 is used it represents the amplification of the loudspeaker amplifier. EN Interface Enable 0: AFE interface disabled 1: AFE interface enabled
Semiconductor Group
122
10.97
PSB 4860
Detailed Register Description 04h R IFS1 15
HP I1 I2 I3
Interface Select 1 0 Reset Value
0
0
0
0
The signal selection fields I1, I2 and I3 of IFS1 determine the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal. The HP bit enables a high-pass for the incoming signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line in signal. HP High-Pass for S1 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for IG2 Input signal 2 for IG2 Input signal 3 for IG2
Note: As all sources are always active, unused sources must be set to 0 (S0).
Semiconductor Group
123
10.97
PSB 4860
Detailed Register Description 05h R IFG1 15
0 IG1
Interface Gain 1 0 Reset Value
0
8192 (0 dB)
IFG1 is associated with the incoming signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line in signal. IG1 In order to obtain a gain G the parameter IG1 can be calculated by the following formula: IG1 = 32768 x10
( G - 12.04 dB ) 20 dB
Semiconductor Group
124
10.97
PSB 4860
Detailed Register Description 06h R IFG2 15
0 IG2
Interface Gain 2 0 Reset Value
0
8192 (0 dB)
IFG2 is associated with the outgoing signal of channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal. IG2 Gain of Amplifier IG2 IG2 = 32768 x10
( G - 12.04 dB ) 20 dB
In order to obtain a gain G the parameter IG2 can be calculated by the following formula:
Semiconductor Group
125
10.97
PSB 4860
Detailed Register Description 07h R IFS2 15
HP I1 I2 I3
Interface Select 2 0 Reset Value
0
0
0
0
The signal selection fields I1, I2 and I3 of IFS2 determine the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal. The HP bit enables a high-pass for the incoming signal of channel 2 of the analog interface. For the PSB 4851 this is usually the microphone signal. HP High-Pass for S3 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for IG4 Input signal 2 for IG4 Input signal 3 for IG4
Note: As all sources are always active, unused sources must be set to 0 (S0).
Semiconductor Group
126
10.97
PSB 4860
Detailed Register Description 08h R IFG3 15
0 IG3
Interface Gain 3 0 Reset Value
0
8192 (0 dB)
IFG3 is associated with the incoming signal of channel 2 of the analog interface. For the PSB 4851 this is usually the microphone signal. IG3 Gain of Amplifier IG3 IG3 = 32768 x10
( G - 12.04 dB ) 20 dB
In order to obtain a gain G the parameter IG3 can be calculated by the following formula:
Semiconductor Group
127
10.97
PSB 4860
Detailed Register Description 09h R IFG4 15
0 IG4
Interface Gain 4 0 Reset Value
0
8192 (0 dB)
IFG4 is associated with the outgoing signal of channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker signal. IG4 Gain of Amplifier IG4 IG4 = 32768 x10
( G - 12.04 dB ) 20 dB
In order to obtain a gain G the parameter IG4 can be calculated by the following formula:
Semiconductor Group
128
10.97
PSB 4860
Detailed Register Description 0Ah R SDCONF 15
0 0 NTS 0 0 0 0 0 DCL 0
Serial Data Interface Configuration 0
EN
Reset Value
0 0 0 0 0 0 0 0 0 0 0
NTS
Number of Timeslots
13 0 0 ... 1 12 0 0 ... 1 11 0 0 ... 1 10 0 0 ... 1 9 0 0 ... 1 8 0 1 ... 1 Description 1 2 ... 64
DCL
Double Clock Mode 0: Single Clock Mode 1: Double Clock Mode
EN
Enable Interface 0: Interface is disabled (both channels) 1: Interface is enabled (depending on separate channel enable bits)
Semiconductor Group
129
10.97
PSB 4860
Detailed Register Description 0Bh R SDCHN1 15
NAS 0 0 PCD EN PCM DD TS
Serial Data Interface Channel 1 0 Reset Value
0
0
0
0
0
0
0
0
NAS
Number of active DRST strobe (SSDI interface mode)
15 0 ... 1 14 0 ... 1 13 0 ... 1 12 0 ... 1 Description 1 ... 16
PCD
PCM Code 0: A-law 1: -law
EN
Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1
PCM
PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot)
DD
Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DU: Data Downstream
TS
Timeslot for Channel 1
5 0 ... 1 4 0 ... 1 3 0 ... 1 2 0 ... 1 1 0 ... 1 0 0 ... 1 Description 0 ... 63
Semiconductor Group
130
10.97
PSB 4860
Detailed Register Description
Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case.
Semiconductor Group
131
10.97
PSB 4860
Detailed Register Description 0Ch R IFS3 15
HP I1 I2 I3
Interface Select 3 0 Reset Value
0
0
0
0
The signal selection fields I1, I2 and I3 of IFS3 determine the outgoing signal of channel 1 of the IOM/SSDI-interface. The HP bit enables a high-pass for the incoming signal of channel 1 of the analog IOM/ SSDI-interface. HP High-Pass for S6 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for S5 Input signal 2 for S5 Input signal 3 for S5
Note: As all sources are always active, unused sources must be set to 0 (S0).
Semiconductor Group
132
10.97
PSB 4860
Detailed Register Description 0Dh R SDCHN2 15
0 0 0 0 0 0 PCD EN PCM DD TS
Serial Data Interface Channel 2 0 Reset Value
0
0
0
0
0
0
0
0
0
0
0
PCD
PCM Code 0: A-law 1: -law
EN
Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1
PCM
PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot)
DD
Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DD: Data Downstream
TS
Timeslot for Channel 2
5 0 0 ... 1 4 0 0 ... 1 3 0 0 ... 1 2 0 0 ... 1 1 0 0 ... 1 0 0 1 ... 1 Description 0 1 ... 63
Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case.
Semiconductor Group
133
10.97
PSB 4860
Detailed Register Description 0Eh R IFS4 15
HP I1 I2 I3
Interface Select 4 0 Reset Value
0
0
0
0
The signal selection fields I1, I2 and I3 of IFS4 determine the outgoing signal of channel 2 of the IOM/SSDI-interface. The HP bit enables a high-pass for the incoming signal of channel 2. HP High-Pass for S7 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for S8 Input signal 2 for S8 Input signal 3 for S8
As all sources are always active, unused sources must be set to 0 (S0).
Semiconductor Group
134
10.97
PSB 4860
Detailed Register Description 0Fh R IFG5 15
ATT1 ATT2
Interface Gain 5 0 Reset Value
255 (0 dB) 255 (0 dB)
ATT1
Attenuation for I3 (Channel 1)
In order to obtain an attenuation A the parameter ATT1 can be calculated by the following formula: ATT1 = 256 x10 ATT2 Attenuation for I3 (Channel 2)
A 20 dB
In order to obtain an attenuation A the parameter ATT2 can be calculated by the following formula: ATT2 = 256 x10
A 20 dB
Semiconductor Group
135
10.97
PSB 4860
Detailed Register Description 10h R UA 15
ATT 0 0 0 I1
Universal Attenuator 0 Reset Value
0 (-100 dB) 0 0 0 0
ATT
Attenuation for UA
For a given attenuation A [dB] the parameter ATT can be calculated by the following formula: ATT = 256 x10 I1 Input Selection for UA
A 20 dB
Semiconductor Group
136
10.97
PSB 4860
Detailed Register Description 11h R DGCTL 15
EN MD 0 0 0 0 0 0 0 0 0 0 DTC
DTMF Generator Control 0 Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
Generator Enable 0: Disabled 1: Enabled
MD
Mode 0: raw 1: cooked
DTC
Dial Tone Code (cooked mode)
3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Digit 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Frequency 697/1209 697/1336 697/1477 697/1633 770/1209 770/1336 770/1477 770/1633 852/1209 852/1336 852/1477 852/1633 941/1209 941/1336 941/1477 941/1633
Semiconductor Group
137
10.97
PSB 4860
Detailed Register Description 12h 15
0 FRQ
DGF1
DTMF Generator Frequency 1 0
FRQ
Frequency of Generator 1
The parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: f FRQ = 32768 x -----------------4000Hz
Semiconductor Group
138
10.97
PSB 4860
Detailed Register Description 13h 15
0 FRQ
DGF2
DTMF Generator Frequency 2 0
FRQ
Frequency of Generator 2
he parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: f FRQ = 32768 x -----------------4000Hz
Semiconductor Group
139
10.97
PSB 4860
Detailed Register Description 14h 15
0 LEV2 0 LEV1
DGL
DTMF Generator Level 0
LEV2
Signal Level of Generator 2
In order to obtain a signal level L (relative to the PCM maximum value) for generator 2 the value of LEV2 can be calculated according to the following formula: LEV2 = 128 x10
L 20 dB
LEV1
Signal Level of Generator 1
In order to obtain a signal level L (relative to the PCM maximum value) for generator 1 the value of LEV1 can be calculated according to the following formula: LEV1 = 128 x10
L 20 dB
Semiconductor Group
140
10.97
PSB 4860
Detailed Register Description 15h 15
ATT2 ATT1
DGATT
DTMF Generator Attenuation 0
ATT2
Attenuation of Signal S10 128 + 1024 x10 ATT2 = A 20 dB 128 x10
A 20 dB
In order to obtain attenuation A the parameter ATT2 can be calculated by the formula: ;A > 18, 1 dB ;A < 18, 1 dB
ATT1
Attenuation of Signal S9 128 + 1024 x10 ATT1 = A 20 dB 128 x10
A 20 dB
In order to obtain attenuation A the parameter ATT1 can be calculated by the formula: ;A > 18, 1 dB ;A < 18, 1 dB
Semiconductor Group
141
10.97
PSB 4860
Detailed Register Description 16h R CNGCTL 15
EN 0 0 0 0 0 0 0 0 0 0 I1
Calling Tone Control 0 Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
EN
Enable 0: CNG unit disabled 1: CNG unit enabled
I1
Input Selection for Calling Tone Detector
Semiconductor Group
142
10.97
PSB 4860
Detailed Register Description 17h 15
0 TIME
CNGBT
CNG Burst Time 0
TIME
Minimum Time for Calling Tone
In order to obtain the parameter TIME for a minimum time t the following formula can be used: TIME = t 0.125 ms
Semiconductor Group
143
10.97
PSB 4860
Detailed Register Description 18h 15
0 0 MIN
CNGLEV
CNG Minimal Signal Level 0
MIN
Minimum Signal Level for Calling Tone
In order to obtain the parameter MIN for a minimum signal level L the following formula can be used: MIN = 16384 x10
L 20 dB
Semiconductor Group
144
10.97
PSB 4860
Detailed Register Description 19h 15
1 1 1 1 RES
CNGRES
CNG Signal Resolution 0
RES
Signal Resolution
L 20 dB
The parameter RES depends on the noise level L as follows: RES = - 4096 x10
Semiconductor Group
145
10.97
PSB 4860
Detailed Register Description 1Ah R ATDCTL0 15
EN 0 0 I1 0 0 0 0 0 0 ATC
Alert Tone Detection 0 0 Reset Value
0
1)
0
0
0
0
0
0
0
0
0
-1)
undefined
EN
Enable alert tone detection 0: The alert tone detection is disabled 1: The alert tone detection is enabled
I1 ATC
Input signal selection Alert Tone Code
1 0 0 1 1 0 0 1 0 1 Description no tone 2130 2750 2130/2750
Semiconductor Group
146
10.97
PSB 4860
Detailed Register Description 1Bh 15
MD 0 0 DEV 0 0 0 0 MIN
ATDCTL1
Alert Tone Detection 1 0
MD
Alert tone detection mode 0: Only dual tones will be detected 1: Either dual or single tones will be detected
DEV
Maximum frequency deviation for alert tone 0: 0.5% 1: 1.1%
MIN
Minimum level of alert tone signal
min 20 dB
For a minimum signal level min the parameter MIN is given by the following formula: MIN = 2560 x10
Semiconductor Group
147
10.97
PSB 4860
Detailed Register Description 1Ch R CIDCTL0 15
EN 0 0 I1 DATA
Caller ID Control 0 0 Reset Value
0
0
0
0
0
EN
CID Enable 0: Disabled 1: Enabled
I1 DATA
Input signal selection Last received data byte
Semiconductor Group
148
10.97
PSB 4860
Detailed Register Description 1Dh 15
NMB NMSS MIN
CIDCTL1
Caller ID Control 1 0
NMB
Minimum Number of Mark Bits
15 0 0 ... 1 14 0 0 ... 1 13 0 0 ... 1 ... 1 ... 1 12 0 11 0 10 0 1 ... 1 Description 0 10 ... 630
NMSS Minimum Number of Mark/Space Sequences
9 0 0 ... 1 8 0 0 ... 1 7 0 0 ... 1 6 0 0 ... 1 5 0 1 ... 1 311 Description 1 11
MIN
Minimum Signal Level for CID Decoder
min 20 dB
For a minimum signal level min the parameter MIN is given by the following formula: MIN = 640 x10
Semiconductor Group
149
10.97
PSB 4860
Detailed Register Description 20h R CPTCTL 15
EN MD 0 0 0 0 0 0 0 0 0 I1
Call Progress Tone Control 0 Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
EN
CPT Detector Enable 0: Disabled 1: Enabled
MD
CPT Mode 0: raw 1: cooked
I1
Input signal selection
Semiconductor Group
150
10.97
PSB 4860
Detailed Register Description 21h 15
NUM 0 SN MIN
CPTTR
Call Progress Tone Thresholds 0
NUM
Number of Cycles
15 0 0 ... 1 14 0 0 ... 1 13 0 1 ... 1 cooked mode reserved 2 ... 8 raw mode 0 reserved reserved reserved
SN
Minimal Signal-to-Noise Ratio
11 1 1 0 0 0 10 1 0 1 0 0 9 1 0 0 1 0 8 1 0 0 0 0 Description 9 dB 12 dB 15 dB 18 dB 22 dB
MIN
Minimum Signal Level for CPT Detector
Value 89h 85h 80h 9Ah 95h 90h Description -40 dB -42 dB -44 dB -46 dB -48 dB -50 dB
Semiconductor Group
151
10.97
PSB 4860
Detailed Register Description 22h 15
MINB MING
CPTMN
CPT Minimum Times 0
MINB
Minimum Time for CPT Burst
The parameter MINB for a minimal burst time TBmin can be calculated by the following formula: TBmin - 32 ms MINB = ------------------------------------4 MING Minimum Time for CPT Gap
The parameter MING for a minimal burst time TGmin can be calculated by the following formula: TGmin - 32 ms MING = ------------------------------------4
Semiconductor Group
152
10.97
PSB 4860
Detailed Register Description 23h 15
MAXB MAXG
CPTMX
CPT Maximum Times 0
MAXB Maximum Time for CPT Burst The parameter MAXB for a maximal burst time of TBmax can be calculated by the following formula: TBmax - TBmin MAXB = ---------------------------------------8 MAXG Maximum Time for CPT Gap The parameter MAXG for a maximal burst time of TGmax can be calculated by the following formula: TGmax - TGmin MAXG = ----------------------------------------8
Semiconductor Group
153
10.97
PSB 4860
Detailed Register Description 24h 15
DIFB DIFG
CPTDT
CPT Delta Times 0
DIFB
Maximum Time Difference between consecutive Bursts
The parameter DIFB for a maximal difference of t ms of two burst durations can be calculated by the following formula: t DIFB = ---------2 ms DIFG Maximum Time Difference between consecutive Gaps
The parameter DIFG for a maximal difference of t ms of two gap durations can be calculated by the following formula: t DIFG = ---------2 ms
Semiconductor Group
154
10.97
PSB 4860
Detailed Register Description 25h R LECCTL 15
EN MD 0 0 0 0 I1 I2
Line Echo Cancellation Control 0 Reset Value
0
0
0
0
0
0
0
0
EN
Enable 0: Disabled 1: Enabled
MD
Mode 0: Normal 1: Extended
I1 I2
Input signal selection for I1 Input signal selection for I2
Semiconductor Group
155
10.97
PSB 4860
Detailed Register Description 26h 15
0 MIN
LECLEV
Minimal Signal Level for Line Echo Cancellation 0
MIN The parameter MIN for a minimal signal level L (dB) can be calculated by the following formula: 512 x ( 96.3 + L ) MIN = --------------------------------------5 x log2
Semiconductor Group
156
10.97
PSB 4860
Detailed Register Description 27h 15
0 ATT
LECATT
Externally Provided Attenuation 0
ATT The parameter ATT for an externally provided attenuation A (dB) can be calculated by the following formula: 512 x A ATT = ------------------5 x log2
Semiconductor Group
157
10.97
PSB 4860
Detailed Register Description 28h 15
0 MGN
LECMGN
Margin for Double Talk Detection 0
MGN The parameter MGN for a margin of L (dB) can be calculated by the following formula: 512 x L MGN = ------------------5 x log2
Semiconductor Group
158
10.97
PSB 4860
Detailed Register Description 29h R DDCTL 15
EN 0 0 I1 0 0 0 DTC
DTMF Detector Control 0 Reset Value
0
1)
0
0
0
0
0
0
-1)
undefined
EN
Enable DTMF tone detection 0: The DTMF detection is disabled 1: The DTMF detection is enabled
I1 DTC
Input signal selection DTMF Tone Code
4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency 941 / 1633 697 / 1209 697 / 1336 697 / 1477 770 / 1209 770 / 1336 770 / 1477 852 / 1209 852 / 1336 852 / 1477 941 / 1336 941 / 1209 941 / 1477 697 / 1633 770 / 1633 852 / 1633 Digit D 1 2 3 4 5 6 7 8 9 0 * # A B C
Semiconductor Group
159
10.97
PSB 4860
Detailed Register Description 2Ah 15
0 TWIST
DDTW
DTMF Detector Signal Twist 0
TWIST Signal twist for DTMF tone In order to obtain a minimal signal twist T the parameter TWIST can be calculated by the following formula: TWIST = 32768 x10
( 0.5 dB - T ) 10 dB
Note: TWIST must be in the range [4096,20480]
Semiconductor Group
160
10.97
PSB 4860
Detailed Register Description 2Bh 15
1 1 1 1 1 1 1 1 1 1 MIN
DDLEV
DTMF Detector Minimum Signal Level 0
MIN
Minimum Signal Level
5 0 0 ... 1 1 4 0 0 ... 0 0 3 1 1 ... 0 0 2 1 1 ... 0 0 1 1 1 ... 0 1 0 0 1 ... 1 0 Description -50 dB -49 dB ... -31 dB -30 dB
Note: Values outside the given range are reserved and must not be used.
Semiconductor Group
161
10.97
PSB 4860
Detailed Register Description 2Eh R FCFCTL 15
EN 0 ADR 0 0 0 I
Equalizer Control 0 Reset Value
0
0
0
0
0
0
0
EN
Enable equalizer 0: The equalizer is disabled 1: The equalizer is enabled
ADR
Coefficient address
13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Coefficient A1 A2 A3 A4 A5 A6 A7 A8 A9 B2 B3 B4 B5 B6 B7 B8 B9 C1 D1 D2 D3 D4 D5
Semiconductor Group
162
10.97
PSB 4860
Detailed Register Description
13 0 0 0 0 0 0 0 0 0 1 1 1 1 12 1 1 1 1 1 1 1 1 1 0 0 0 0 11 0 1 1 1 1 1 1 1 1 0 0 0 0 10 1 0 0 0 0 1 1 1 1 0 0 0 0 9 1 0 0 1 1 0 0 1 1 0 0 1 1 8 1 0 1 0 1 0 1 0 1 0 1 0 1 Coefficient D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 C2
I1
Input signal selection
Semiconductor Group
163
10.97
PSB 4860
Detailed Register Description 2Fh 15
V
FCFCOF
Equalizer Coefficient Data 0
V
Coefficient value
For the coefficient A1-A9, B2-B9 and D1-D17 the following formula can be used to calculate V for a coefficient c: V = 32768 x c ; -1 c < 1 For the coefficients C1 and C2 the following formula can be used to calculate V for a coefficient c: V = 128 x c ; 1 c < 256
Semiconductor Group
164
10.97
PSB 4860
Detailed Register Description 30h R SCCTL 15
EN HQ VC 0 0 0 I1 I2
Speech Coder Control 0 Reset Value
0
0
0
0
0
0
0
0
EN
Enable 0: Disabled 1: Enabled
HQ
High Quality Mode 0: Long Play Mode 1: High Quality Mode
VC
Voice Controlled Start of Recording 0: Disabled 1: Enabled
I1 I2
Input signal selection (first input) Input signal selection (second input)
Semiconductor Group
165
10.97
PSB 4860
Detailed Register Description 31h 15
TIME MIN
SCCT2
Speech Coder Control 2 0
TIME The parameter TIME for a time t ([ms]) can be calculated by the following formula: t TIME = ----32 MIN The parameter MIN for a signal level L ([dB]) can be calculated by the following formula: MIN = 16384 x10
L ----20
Semiconductor Group
166
10.97
PSB 4860
Detailed Register Description 32h 15
0 LP 0 0 0 0 0 0 0
SCCT3
Speech Coder Control 3 0
0
LP The parameter LP for a time constant of t ([ms]) can be calculated by the following formula: 256 LP = -------t
Semiconductor Group
167
10.97
PSB 4860
Detailed Register Description 34h R SDCTL 15
EN 0 0 0 0 0 0 0 0 0 0 0 0
Speech Decoder Control 0
SPEED
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN
Enable 0: Disabled 1: Enabled
SPEED Playback Speed
1 0 0 1 1 0 0 1 0 1 Description normal speed 0.5 times normal speed 1.5 times normal speed 2.0 times normal speed
Semiconductor Group
168
10.97
PSB 4860
Detailed Register Description 38h R AGCCTL 15
EN 0 0 0 0 0 I1 I2
AGC Control 0 Reset Value
0
0
0
0
0
0
0
0
EN
Enable 0: Disabled 1: Enabled
I1 I2
Input signal selection for I1 Input signal selection for I2
Semiconductor Group
169
10.97
PSB 4860
Detailed Register Description 39h R AGCATT 15
ATT
Automatic Gain Control Attenuation 0 Reset Value
0 (-100 dB)
ATT The parameter ATT for an attenuation A ([dB]) can be calculated by the following formula:
A ----20
ATT = 32768 x10
Semiconductor Group
170
10.97
PSB 4860
Detailed Register Description 3Ah 15
COM AG_INIT
AGC1
Automatic Gain Control 1 0
COM The parameter COM for a signal level L ([dB]) can be calculated by the following formula:
----------------------- 128 + 10 20 COM = L + 42, 14 ----------------------- 10 20 L + 66, 22
;L < -42,14 dB ;L > -42,14 dB
AG_INIT In order to obtain an initial gain G ([db]) the parameter AG_INIT can be calculated by the following formula: G + 18, 06 ----------------------- ;G < 6, 02 dB 128 + 10 20 AG_INIT = G - 6, 02 -------------------- 10 20 ;G > 6, 02 dB
Semiconductor Group
171
10.97
PSB 4860
Detailed Register Description 3Bh 15
SPEEDL SPEEDH
AGC2
Automatic Gain Control 2 0
SPEEDL The parameter SPEEDL for a multiplication factor M is given by the following formula: M SPEEDL = ----------8192 SPEEDH The parameter SPEEDH for a multiplication factor M is given by the following formula: M SPEEDH = -------256
Semiconductor Group
172
10.97
PSB 4860
Detailed Register Description 3Ch 15
MIN MAX
AGC3
Automatic Gain Control 3 0
MIN The parameter MIN for a gain G ([dB]) can be calculated by the following formula:
----------------------- 128 + 10 20 MIN = G - 6, 02 --------------------10 20 G + 18, 06
;G < 6, 02 dB ;G > 6, 02 dB
MAX The parameter MAX for an attenuation A ([dB]) can be calculated by the following formula: MAX =
A + 42, 14 -----------------------10 20
Semiconductor Group
173
10.97
PSB 4860
Detailed Register Description 3Dh 15
DEC LIM
AGC4
Automatic Gain Control 4 0
DEC The parameter DEC for a time constant t ([1/ms]) is given by the following formula: 256 DEC = -------t LIM The parameter LIM for a signal level L ([dB]) can be calculated by the following formula:
-------------------- 128 + 10 20 LIM = L + 66, 22 -----------------------10 20 L + 90, 3
;L < 66,22 dB ;L > 66,22 dB
Semiconductor Group
174
10.97
PSB 4860
Detailed Register Description 3Eh 15
0 0 0 0 0 0 0 0 1 LP
AGC5
Automatic Gain Control 5 0
LP The parameter LP for a time constant t ([1/ms]) is given by the following formula: 16 LP = ----t
Semiconductor Group
175
10.97
PSB 4860
Detailed Register Description 40h R FCTL 15
0 MD MS TS 0 0 0 0 FNO
File Control 0 Reset Value
0
0
0
0
0
0
0
0
0
MD
Mode 0: Audio Mode 1: Binary Mode
MS
Memory Space 0: R/W Memory 1: Voice Prompt Directory
TS
Time Stamp 0: no update of RTC1/RTC2 entry of file descriptor 1: RTC1/RTC2 entries are updated by content of RTC1/RTC2 registers.
FNO
File Number
Semiconductor Group
176
10.97
PSB 4860
Detailed Register Description 41h R FCMD 15
0 IN RD 0 0 0 0 0 ABT EIE 0 CMD
File Command 0 Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
IN
Initialize 0: no 1: yes (if CMD=1111)
RD
Remap Directory 0: no 1: yes
ABT
Abort Command 0: no 1: abort recompress
EIE
Enable Immediate Execution 0: disabled (default, always possible) 1: enabled (restricted to certain commands and operating modes)
CMD
File Command
4 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 1 1 2 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 Description Open File Activate Seek Cut File Read Data Write Data Memory Status Recompress file Read File Descriptor - User Write File Descriptor - User
Semiconductor Group
177
10.97
PSB 4860
Detailed Register Description
4 0 0 0 0 0 0 1 1 1 1 1 1 1 3 1 1 1 1 1 1 0 0 0 0 0 1 1 2 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 Description Read File Descriptor - RTC1 Read File Descriptor - RTC2 Read File Descriptor - LEN Garbage Collection Open Next Free File Initialize DMA Read DMA Write Erase Block Set Address reserved reserved reserved
Semiconductor Group
178
10.97
PSB 4860
Detailed Register Description 42h R FDATA 15
FREE
File Data 0 Reset Value
0
The FDATA register contains the following information after a memory status command: FREE Free Blocks
Number of blocks (1 kByte) currently usable for recording.
Semiconductor Group
179
10.97
PSB 4860
Detailed Register Description 43h R FPTR 15
File Pointer 0 0 0 0 0 Phrase selector
File Pointer 0
Reset Value
0
Semiconductor Group
180
10.97
PSB 4860
Detailed Register Description 47h R SPSCTL 15
POS 0 0 0 0 0 0 0 MODE SP1
SPS Control 0
SP0
Reset Value
0
1)
0
0
0
0
0
0
0
0
-1)
-1)
undefined
POS
Position of Status Register Window
15 0 0 ... 1 14 0 0 ... 1 13 0 0 ... 1 12 0 1 ... 0 SPS0 Bit 0 Bit 1 ... Bit 14 SPS1 Bit 1 Bit 2 ... Bit 15
MODE Mode of SPS Interface
4 0 0 1 1 1 3 0 0 0 0 1 2 0 1 0 1 0 Description Disabled (SPS0 and SPS1 zero) Output of SP1 and SP0 Output of speakerphone state Expanded address output Output of STATUS register
SP1
Direct Control for SPS1 0: SPS1 set to 0 1: SPS1 set to 1
SP0
Direct Control for SPS0 0: SPS0 set to 0 1: SPS0 set to 1
Note: If mode 1 has been selected prior to power-down, both mode 1 and the values of SP1 and SP0 are retained during power-down and wake-up. Other modes are reset to 0 during power down.
Semiconductor Group 181 10.97
PSB 4860
Detailed Register Description 48h R RTC1 15
0 0 0 0 MIN SEC
Real Time Clock 1 0 Reset Value
0
0
0
0
0
0
MIN
Minutes
Number of minutes elapsed in the current hour (0-59). SEC Seconds
Number of seconds elapsed in the current minute (0-59).
Semiconductor Group
182
10.97
PSB 4860
Detailed Register Description 49h R RTC2 15
DAY HR
Real Time Clock 2 0 Reset Value
0 0
DAY
Days
Number of days elapsed since last reset (0-2047). HR Hours
Number of hours elapsed in the current day (0-23).
Semiconductor Group
183
10.97
PSB 4860
Detailed Register Description 4Ah R DOUT0 15
0 0 0 0 DATA
Data Out (Timeslot 0) 0 Reset Value
0
0
0
0
0
DATA
Output Data
Output data for pins MA0-MA11 while MA12=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
Semiconductor Group
184
10.97
PSB 4860
Detailed Register Description 4Bh R DOUT1 15
0 0 0 0 DATA
Data Out (Timeslot 1) 0 Reset Value
0
0
0
0
0
DATA
Output Data
Output data for pins MA0-MA11 while MA13=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
Semiconductor Group
185
10.97
PSB 4860
Detailed Register Description 4Ch R DOUT2 15
0 0 0 0 DATA
Data Out (Timeslot 2) 0 Reset Value
0
0
0
0
0
DATA
Output Data
Output data for pins MA0-MA11 while MA14=1 (only if HWCONFIG1:APP=10).
Note: This register cannot be read.
Semiconductor Group
186
10.97
PSB 4860
Detailed Register Description 4Dh R DOUT3 15
DATA
Data Out (Timeslot 3 or Static Mode) 0 Reset Value
0
DATA
Output Data
Output data for pins MA0-MA11 while MA15=1 (only if HWCONFIG1:APP=10). Output data for pins MA0-MA15 (only if HWCONFIG1:APP=01)
Note: This register cannot be read.
Semiconductor Group
187
10.97
PSB 4860
Detailed Register Description 4Eh 15
DATA
DIN
Data In (Timeslot 3 or Static Mode) 0
DATA
Input Data
Input data for pins MA0-MA11 at falling edge of MA12 (only if HWCONFIG1:APP=10). Input data for pins MA0-MA15 (only if HWCONFIG1:APP=01)
Semiconductor Group
188
10.97
PSB 4860
Detailed Register Description 4Fh R DDIR 15
DIR
Data Direction (Timeslot 3 or Static Mode) 0 Reset Value
0 (all inputs)
DIR 0: input
Port Direction
Port direction during MA12=1 or in static mode. 1: output
Note: This register cannot be read.
Semiconductor Group
189
10.97
PSB 4860
Detailed Register Description 60h R SCTL 15
ENS ENC 0 0 0 0 0 0 MD SDR SDX 0 0 AGR AGX
Speakerphone Control 0
0
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENS
Enable Echo Suppression 0: The echo suppression unit is disabled 1: The echo suppression unit is enabled
ENC
Enable Echo Cancellation 0: The echo cancellation unit is disabled 1: The echo cancellation unit is enabled
MD
Mode 0: Speakerphone mode 1: Loudhearing mode
SDR
Signal Source of SDR 0: after AGCR 1: before AGCR
SDX
Signal Source of SDX 0: after AGCX 1: before AGCX
AGR
AGCR Enable 0: AGCR disabled 1: AGCR enabled
AGX
AGCX Enable 0: AGCX disabled 1: AGCX enabled
Semiconductor Group
190
10.97
PSB 4860
Detailed Register Description 62h R SSRC1 15
0 0 0 0 0 0 I1 I2
Speakerphone Source 1 0 Reset Value
0
0
0
0
0
0
0
0
I1 I2
Input Signal Selection (Acoustic Source 1) Input Signal Selection (Acoustic Source 2)
Semiconductor Group
191
10.97
PSB 4860
Detailed Register Description 63h R SSRC2 15
0 0 0 0 0 0 I3 I4
Speakerphone Source 2 0 Reset Value
0
0
0
0
0
0
0
0
I3 I4
Input Signal Selection (Line Source 1) Input Signal Selection (Line Source 2)
Semiconductor Group
192
10.97
PSB 4860
Detailed Register Description 64h 15
0 LP2L 0 LIM
SSDX1
Speech Detector (Transmit) 1 0
LP2L The parameter LP2L for a saturation level L (dB) can be calculated by the following formula: 2xL LP2L = ------------------5 x log2 LIM The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be calculated by the following formula: 2 x ( 96.3 + L ) LIM = --------------------------------5 x log2
Semiconductor Group
193
10.97
PSB 4860
Detailed Register Description 65h 15
LP1 0 OFF
SSDX2
Speech Detector (Transmit) 2 0
LP1 The parameter LP1 for a time t (ms) can be calculated by the following formula: 64 t LP1 = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048
OFF The parameter OFF for a level offset of O (dB) can be calculated by the following formula: 2xO OFF = ------------------5 x log2
Semiconductor Group
194
10.97
PSB 4860
Detailed Register Description 66h 15
PDN LP2N
SSDX3
Speech Detector (Transmit) 3 0
PDN The parameter PDN for a time t (ms) can be calculated by the following formula: 64 t PDN = 128 + 2048 t LP2N The parameter LP2N for a time t (ms) can be calculated by the following formula: 64 t LP2N = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048 ;0.5 < t < 64 ;16.2 < t < 2048
Semiconductor Group
195
10.97
PSB 4860
Detailed Register Description 67h 15
PDS 0 LP2S
SSDX4
Speech Detector (Transmit) 4 0
PDS The parameter PDS for a time t (ms) can be calculated by the following formula: 64 t PDS = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048
LP2S The parameter LP2S for a time t (ms) can be calculated by the following formula: 262144 LP2S = ----------------t
Semiconductor Group
196
10.97
PSB 4860
Detailed Register Description 68h 15
0 LP2L 0 LIM
SSDR1
Speech Detector (Receive) 1 0
LP2L The parameter LP2L for a saturation level L (dB) can be calculated by the following formula: 2xL LP2L = ------------------5 x log2 LIM The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be calculated by the following formula: 2 x ( 96.3 + L ) LIM = --------------------------------5 x log2
Semiconductor Group
197
10.97
PSB 4860
Detailed Register Description 69h 15
LP1 0 OFF
SSDR2
Speech Detector (Receive) 2 0
LP1 The parameter LP1 for a time t (ms) can be calculated by the following formula: 64 t LP1 = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048
OFF The parameter OFF for a level offset of O (dB) can be calculated by the following formula: 2xO OFF = ------------------5 x log2
Semiconductor Group
198
10.97
PSB 4860
Detailed Register Description 6Ah 15
PDN LP2N
SSDR3
Speech Detector (Receive) 3 0
PDN The parameter PDN for a time t (ms) can be calculated by the following formula: 64 t PDN = 128 + 2048 t LP2N The parameter LP2N for a time t (ms) can be calculated by the following formula: 64 t LP2N = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048 ;0.5 < t < 64 ;16.2 < t < 2048
Semiconductor Group
199
10.97
PSB 4860
Detailed Register Description 6Bh 15
PDS 0 LP2S
SSDR4
Speech Detector (Receive) 4 0
PDS The parameter PDS for a time t (ms) can be calculated by the following formula: 64 t PDS = 128 + 2048 t ;0.5 < t < 64 ;16.2 < t < 2048
LP2S The parameter LP2S for a time t (ms) can be calculated by the following formula: 262144 LP2S = ----------------t
Semiconductor Group
200
10.97
PSB 4860
Detailed Register Description 6Ch 15
G ET
SSCAS1
Speech Comparator (Acoustic Side) 1 0
G The parameter G for a gain A (dB) can be calculated by the following formula: 2xA G = ------------------5 x log2
Note: The parameter G is interpreted in two's complement.
ET The parameter ET for a time t (ms) can be calculated by the following formula: t ET = -4
Semiconductor Group
201
10.97
PSB 4860
Detailed Register Description 6Dh 15
0 GDN PDN
SSCAS2
Speech Comparator (Acoustic Side) 2 0
GDN The parameter GDN for a gain G (dB) can be calculated by the following formula: 4xG GDN = ------------------5 x log2 PDN The parameter PDN for a decay rate R (ms/dB) can be calculated by the following formula: 64 x R PDN = ------------------5 x log2
Semiconductor Group
202
10.97
PSB 4860
Detailed Register Description 6Eh 15
0 GDS PDS
SSCAS3
Speech Comparator (Acoustic Side) 3 0
GDS The parameter GDS for a gain G (dB) can be calculated by the following formula: 4xG GDS = ------------------5 x log2 PDS The parameter PDS for a decay rate R (ms/dB) can be calculated by the following formula: 64 x R PDS = ------------------5 x log2
Semiconductor Group
203
10.97
PSB 4860
Detailed Register Description 6Fh 15
G ET
SSCLS1
Speech Comparator (Line Side) 1 0
G The parameter G for a gain A (dB) can be calculated by the following formula: 2xA G = ------------------5 x log2
Note: The parameter G is interpreted in two's complement.
ET The parameter ET for a time t (ms) can be calculated by the following formula: t ET = -4
Semiconductor Group
204
10.97
PSB 4860
Detailed Register Description 70h 15
0 GDN PDN
SSCLS2
Speech Comparator (Line Side) 2 0
GDN The parameter GDN for a gain G (dB) can be calculated by the following formula: 4xG GDN = ------------------5 x log2 PDN The parameter PDN for a decay rate R (ms/dB) can be calculated by the following formula: 64 x R PDN = ------------------5 x log2
Semiconductor Group
205
10.97
PSB 4860
Detailed Register Description 71h 15
0 GDS PDS
SSCLS3
Speech Comparator (Line Side) 3 0
GDS The parameter GDS for a gain G (dB) can be calculated by the following formula: 4xG GDS = ------------------5 x log2 PDS The parameter PDS for a decay rate R (ms/dB) can be calculated by the following formula: 64 x R PDS = ------------------5 x log2
Semiconductor Group
206
10.97
PSB 4860
Detailed Register Description 72h 15
0 ATT SW
SATT1
Attenuation Unit 1 0
ATT The parameter ATT for an attenuation A (dB) can be calculated by the following formula: 2xA ATT = ------------------5 x log2
SW The parameter SW for a switching rate R (ms/dB) can be calculated by the following formula: 1 128 + ---------------------------------5 x log2 x SW SW = 16 --------------------------------- 5 x log2 x SW ;0.0053 < SW < 0.66 ;0.66 < SW < 0.63
Semiconductor Group
207
10.97
PSB 4860
Detailed Register Description 73h 15
TW DS
SATT2
Attenuation Unit 2 0
TW The parameter TW for a time t (ms) can be calculated by the following formula: t TW = ----16 DS The parameter DS for a decay rate R (ms/dB) can be calculated by the following formula: 5 x log2 x R - 1 DS = -------------------------------------4
Semiconductor Group
208
10.97
PSB 4860
Detailed Register Description 74h 15
AG_INIT 0 COM
SAGX1
Automatic Gain Control (Transmit) 1 0
AG_INIT The parameter AG_INIT for a gain G (dB) can be calculated by the following formula: -2 x G AG_INIT = ------------------5 x log2 This parameter is interpreted in two's complement. COM The threshold COM for a level L (dB) can be calculated by the following formula: 2 x ( 96.3 + L ) COM = --------------------------------5 x log2
Semiconductor Group
209
10.97
PSB 4860
Detailed Register Description 75h 15
0 AG_ATT SPEEDH
SAGX2
Automatic Gain Control (Transmit) 2 0
AG_ATT The parameter AG_ATT for a gain G (dB) can be calculated by the following formula: -2 x G AG_ATT = ------------------5 x log2
SPEEDH The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the following formula: 4096 SPEEDH = ------------DxR The variable D denotes the aberration (dB).
Semiconductor Group
210
10.97
PSB 4860
Detailed Register Description 76h 15
AG_GAIN SPEEDL
SAGX3
Automatic Gain Control (Transmit) 3 0
AG_GAIN The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula: -2 x G AG_GAIN = ------------------5 x log2 SPEEDL The parameter COM for a gain G (dB) can be calculated by the following formula: 2 x ( 96.3 + G ) COM = ---------------------------------5 x log2 The variable D denotes the aberration (dB).
Semiconductor Group
211
10.97
PSB 4860
Detailed Register Description 77h 15
0 NOIS 0 LPA
SAGX4
Automatic Gain Control (Transmit) 4 0
NOIS The parameter NOIS for a threshold level L (dB) can be calculated by the following formula: 2 x ( 96.3 + L ) COM = --------------------------------5 x log2 LPA The parameter LPA for a low pass time constant T (mS) can be calculated by the following formula: 16 LPA = ----T
Semiconductor Group
212
10.97
PSB 4860
Detailed Register Description 78h 15
AG_CUR 0 0 0 0 0 0 0
SAGX5
Automatic Gain Control (Transmit) 5 0
0
AG_CUR The current gain G of the AGC can be derived from the parameter Parameter AG_CUR by the following formula: - 5 x log2 x AG_CUR G = ---------------------------------------------------2 AG_CUR is interpreted in two's complement.
Semiconductor Group
213
10.97
PSB 4860
Detailed Register Description 79h 15
AG_INIT 0 COM
SAGR1
Automatic Gain Control (Receive) 1 0
AG_INIT The parameter AG_INIT for a gain G (dB) can be calculated by the following formula: -2 x G AG_INIT = ------------------5 x log2 This parameter is interpreted in two's complement. COM The parameter COM for a threshold L (dB) can be calculated by the following formula: 2 x ( 96.3 + L ) COM = --------------------------------5 x log2
Semiconductor Group
214
10.97
PSB 4860
Detailed Register Description 7Ah 15
0 AG_ATT SPEEDH
SAGR2
Automatic Gain Control (Receive) 2 0
AG_ATT The parameter AG_ATT for a gain G (dB) can be calculated by the following formula: -2 x G AG_ATT = ------------------5 x log2
SPEEDH The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the following formula: 4096 SPEEDH = ------------DxR The variable D denotes the aberration (dB).
Semiconductor Group
215
10.97
PSB 4860
Detailed Register Description 7Bh 15
AG_GAIN SPEEDL
SAGR3
Automatic Gain Control (Receive) 3 0
AG_GAIN The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula: -2 x G AG_GAIN = ------------------5 x log2 SPEEDL The parameter SPEEDL for the regulation speed R (ms/dB) can be calculated by the following formula: 4096 SPEEDL = ------------DxR The variable D denotes the aberration (dB).
Semiconductor Group
216
10.97
PSB 4860
Detailed Register Description 7Ch 15
0 NOIS 0 LPA
SAGR4
Automatic Gain Control (Receive) 4 0
NOIS The parameter NOIS for a threshold level L (dB) can be calculated by the following formula: 2 x ( 96.3 + L ) COM = --------------------------------5 x log2 LPA The parameter LPA for a low pass time constant T (mS) can be calculated by the following formula: 16 LPA = ----T
Semiconductor Group
217
10.97
PSB 4860
Detailed Register Description 7Dh 15
AG_CUR 0 0 0 0 0 0 0
SAGR5
Automatic Gain Control (Receive) 5 0
0
AG_CUR The current gain G of the AGC can be derived from the parameter Parameter AG_CUR by the following formula: - 5 x log2 x AG_CUR G = ---------------------------------------------------2 AG_CUR is interpreted in two's complement.
Semiconductor Group
218
10.97
PSB 4860
Detailed Register Description 7Eh 15
0 LGAR 0 LGAX
SLGA
Line Gain 0
LGAR The parameter LGAR for a gain G (dB) is given by the following formula: LGAR = 128 x10 LGAX The parameter LGAX for a gain G (dB) is given by the following formula: LGAX = 128 x10
( G - 12 ) 20 ( G - 12 ) 20
Semiconductor Group
219
10.97
PSB 4860
Detailed Register Description 80h 15
0 0 0 0 0 0 0 LEN
SAELEN
Acoustic Echo Cancellation Length 0
LEN LEN denotes the number of FIR-taps used.
Semiconductor Group
220
10.97
PSB 4860
Detailed Register Description 81h 15
0 ATT
SAEATT
Acoustic Echo Cancellation Double Talk Attenuation 0
ATT The parameter ATT for an attenuation A (dB) is given by the following formula: 512 x A ATT = ------------------5 x log2
Semiconductor Group
221
10.97
PSB 4860
Detailed Register Description 82h 15
0 0 0 0 0 0 0 0 0 0 0 0 0 GS
SAEGS
Acoustic Echo Cancellation Global Scale 0
GS All coefficients of the FIR filter are scaled by a factor C. This factor is given by the following equation: C=2
GS
Semiconductor Group
222
10.97
PSB 4860
Detailed Register Description 83h 15
0 0 0 0 0 0 0 0 0 0 0 0 0 PS
SAEPS1
Acoustic Echo Cancellation Partial Scale 0
PS The additional scaling coefficient AC is given by the following formula: AC = 2
PS
Semiconductor Group
223
10.97
PSB 4860
Detailed Register Description 84h 15
0 0 0 0 0 0 0 0 0 0 0 0 0 FB
SAEPS2
Acoustic Echo Cancellation First Block 0
FB The parameter FB denotes the first block that is affected by the partial scaling coefficient. If the partial coefficient is one, FB is disregarded.
Semiconductor Group
224
10.97
PSB 4860
Electrical Characteristics 4
Electrical Characteristics Electrical Characteristics
Electrical Characteristics Absolute Maximum Ratings
Symbol Limit Values Unit
4.1
Parameter
Ambient temperature under bias Storage temperature Supply Voltage Supply Voltage Supply Voltage Voltage of pin with respect to ground: XTAL1, XTAL2 Voltage on any pin with respect to ground
TA TSTG VDD VDDA VDDP VS VS
-20 to 85 - 65 to125 -0.5 to 4.2 -0.5 to 4.2 -0.5 to 6 0 to VDDA If VDDP < 3 V: - 0.4 to VDD + 0.5 If VDDP > 3 V: - 0.4 to VDDP + 0.5
C C V V V V V
ESD integrity (according MIL-Std. 883D, method 3015.7): 2 kV Exception: The pins INT, SDX, DU/DX, DD/DR, SPS0, SPS1 and MD0-MD7 are not protected against voltage stress >1 kV.
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
4.2 DC Characteristics
VDD/VDDA = 3.3 V 0.3 V; VDDP = 5 V 10%; VSS/VSSA = 0 V; TA = 0 to 70 C Parameter Input leakage current H-input level (except MA0-MA15, XTAL1,OSC1) H-input level (OSC1) Symbol min. IIL VIH1 VIH2 - 1.0 2.0 0.8 VDD 2.0 - 0.3 Limit Values typ. max. 1.0 VDDP + 0.3 VDDA + 0.3 VDD 0.8 A V V V V 0 V VIN VDD Unit Test Condition
H-input level (MA0-MA15, MCTL1)) VIH3 L-input level (except pins XTAL1,OSC1) Semiconductor Group VIL1
225
10.97
PSB 4860
Electrical Characteristics
VDD/VDDA = 3.3 V 0.3 V; VDDP = 5 V 10%; VSS/VSSA = 0 V; TA = 0 to 70 C Parameter L-input level (OSC1) H-output level (except DU/DX, DD/DR, MA0-MA15, SPS0, SPS1, MD0-MD7) Symbol min. VIL2 VOH1 - 0.3 VDD - 0.45 VDD - 0.6 VDD - 0.45 VDD - 0.6 0.45 0.45 50 25 150 65 240 120 0.45 350 750 1300 10 15 10 20 55 1 50 70 70 10 Limit Values typ. max. 0.2 VDDA V V IO = 2 mA Unit Test Condition
H-output level (SPS0, SPS1, MD0- VOH2 MD7, SDX, INT) H-output level (MA0-MA15) H-output level (DU/DX, DD/DR) L-output level (except DU/DX, DD/DR, MA0-MA15) L-output level (MA0-MA15) (address mode or APP output) L-output current (MA0-MA15) (after reset) H-output current (MCTL1)) L-output level (pins DU/DX, DD/ DR) Internal pullup current (FRDY) Input capacitance Output capacitance VOH3 VOH4 VOL1 VOL2 ILO IHO VOL3 ILI CI CO
V V V V V A A V A pF pF A A mA A
IO = 2 mA IO = 5 mA IO = 7 mA IO = - 2 mA IO = - 5 mA RST=1 RST=1 IO = - 7 mA
VDD supply current IDDS1 (power down, no refresh, no RTC) VDD supply current (power down, refresh, RTC) VDD supply current operating VDDP supply current
1)
IDDS2 IDDO IDDP
VDD = 3.3 V
MCTL signals are (W/FWE, VPRD/FCLE, RAS/FOE, CAS0/ALE, CAS1/FCS)
Semiconductor Group
226
10.97
PSB 4860
Electrical Characteristics 4.3 AC Characteristics
Digital inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The ACtesting input/output waveforms are shown below.
Figure 69 Input/Output Waveforms for AC-Tests
Semiconductor Group
227
10.97
PSB 4860
Electrical Characteristics
DTMF Detector
Parameter Frequency deviation accept Frequency deviation reject Acceptance level Rejection level Twist deviation accept Noise Tolerance Signal duration accept Signal duration reject Gap duration accept 18 40 23 +/-2 Symbol min. -1.5 3.5 -45 Limit Values typ. max. 1.5 -3.5 0 -50 +/-8 12 % % dB dB dB dB ms ms ms rel. to max. PCM rel. to max. PCM programmable Unit Test Condition
CPT Detector
Parameter Frequency acceptance range Frequency rejection range Acceptance level Rejection level Signal duration accept Signal duration reject 50 10 Symbol min. 300 800 -45 Limit Values typ. max. 640 200 0 -50 Hz Hz dB dB ms ms rel. to max. PCM rel. to max. PCM programmable Unit Test Condition
Caller ID Decoder
Parameter Frequency deviation accept Acceptance level Transmission rate Noise Tolerance Symbol min. -2 -45 1188 1200 Limit Values typ. max. 2 0 1212 -12 % dB baud dB rel. to max. PCM Unit Test Condition
Semiconductor Group
228
10.97
PSB 4860
Electrical Characteristics Alert Tone Detector
Parameter Frequency deviation accept Frequency deviation accept Frequency deviation reject Acceptance level Rejection level Twist deviation accept Noise Tolerance Signal duration accept Gap duration accept 75 40 Symbol min. -0.5 -1.1 3.5 -40 Limit Values typ. max. 0.5 1.1 -3.5 0 -5 +/-7 20 % % % dB dB dB dB ms ms rel. to max. PCM rel. to acceptance level ATDCTL1:DEV=0 ATDCTL1:DEV=1 Unit Test Condition
CNG Detector
Parameter Frequency deviation accept Frequency deviation reject Acceptance level Acceptance level Rejection level Signal duration reject Symbol min. -40 -50 -45 -50 -3 dB -1 Limit Values typ. max. 40 50 0 0 Hz Hz dB dB dB % SNR >10 dB SNR >15 dB rel. to CNGLEV:MIN rel. to CNGBT:TIME Unit Test Condition
Semiconductor Group
229
10.97
PSB 4860
Electrical Characteristics Status Register Update Time The individual bits of the STATUS register may change due to an event (like a recognized DTMF tone) or a command. The timing can be divided into four classes Table 87 Class Min. I A D E
1)
Status Register Update Timing Timing Max. 0 125 s1) 250 s Immediately after command has been issued Command has been accepted Deactivation time after command has been issued Associated event has happened 0 0 125 S Comment
one FSC period
With these definitions the timing of the individual bits in the STATUS register can be given as shown in table: Bit 0->1 1->0
1)
Timing Diagrams
RDY A I
ABT E A
CIA E A,D
CD E E,D
CPT E E,D
CNG E D
SD E E,D
ERR E A
BSY A1) E
DTV E E,D
ATV E E,D
up to 30 ms if command is either SDCTL:EN=1 or SCCTL:EN=1
Semiconductor Group
230
10.97
PSB 4860
Electrical Characteristics
CL1 XTAL1
CL2 OSC1
X1 CL1 XTAL2 CL2
X2
OSC2
Figure 70 Oscillator Circuits Recommended Values Oscillator Circuits Load CL1 Static capacitance X1 Motional capacitance X1 Resonance resistor X1 Load CL2 Static Capacitance X2 Motional capacitance X2 Resonance resistor X2 Frequency deviation 1.7 3.5 18 40 100 Value Min Typ 5 17 60 30 Max 40 pF pF fF pF pF fF k ppm Unit
Semiconductor Group
231
10.97
PSB 4860
Electrical Characteristics
t1 t2
DCL
t3
t4
DD/DR
t5
DU/DX
first bit
last bit
t6
t7
DU/DX
bit n
bit n+1
t8
Figure 71 SSDI/IOM(R)-2 Interface - Bit Synchronization Timing
DCL
t9
FSC
t10
t9
t10
Figure 72 SSDI/IOM(R)-2 Interface - Frame Synchronization Timing Parameter SSDI/IOM(R)-2 Interface DCL period DCL high DCL low Input data setup Symbol t1 t2 t3 t4 Limit values Min 90 35 35 20 Max ns ns ns ns Unit
Semiconductor Group
232
10.97
PSB 4860
Electrical Characteristics Parameter SSDI/IOM(R)-2 Interface Input data hold Output data from high impedance to active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC setup FSC hold FSC jitter (deviation per frame) Symbol t5 t6 t7 t8 t9 t10 40 40 -200 200 Limit values Min 20 30 30 30 Max ns ns ns ns ns ns ns Unit
Semiconductor Group
233
10.97
PSB 4860
Electrical Characteristics
DCL
t1
DXST
t2
DRST
t3
t4
t5
t6
FSC
t7
Figure 73 SSDI Interface - Strobe Timing Parameter SSDI Interface DXST delay DRST inactive setup DRST inactive hold DRST active setup DRST active hold FSC setup FSC hold Symbol t1 t2 t3 t4 t5 t6 t7 20 20 20 20 8 40 Limit values Min Max 20 ns ns ns ns ns DCL cycles ns Unit
Semiconductor Group
234
10.97
PSB 4860
Electrical Characteristics
t1 t4
CS
t2
t3
t5
SCLK
t6
SDR
t7 t8 t11
t9
SDX
t10
INT
t12
Figure 74 Serial Control Interface Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time SDR hold time SDX data out delay CS high to SDX tristate SCLK to SDX active SCLK to SDX tristate CS to INT delay Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit values Min 500 100 100 40 10 40 40 80 40 80 40 80 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Semiconductor Group
235
10.97
PSB 4860
Electrical Characteristics
t1 t2
AFECLK
t3
t4
AFEDU
t5
AFEDD
bit n
bit n+1
t6
AFEFS
t7
t7
Figure 75 Analog Front End Interface Parameter AFE Interface AFECLK period AFECLK high AFECLK low AFEDU setup AFEDU hold AFEDD output delay AFEFS output delay Symbol t1 t2 t3 t4 t5 t6 t7 Limit values Min 125 2 2 20 20 30 30 Max 165 ns 1/fXTAL 1/fXTAL ns ns ns ns Unit
Semiconductor Group
236
10.97
PSB 4860
Electrical Characteristics
MA0-MA13
row addr.
t1 t2
col. addr.
RAS
t4 t5 t3 t6
CAS0,CAS1
t7 t8
MD0-MD7
Figure 76 Memory Interface - DRAM Read Access Parameter Memory Interface - DRAM Read Access row address setup time row address hold time column address setup time RAS precharge time RAS to CAS delay CAS pulse width Data input setup time Data input hold time Symbol t1 t2 t3 t4 t5 t6 t7 t8 Limit values Min 50 50 50 110 110 110 40 0 2000 2000 Max ns ns ns ns ns ns ns ns Unit
Semiconductor Group
237
10.97
PSB 4860
Electrical Characteristics
MA0-MA13
row addr.
t1 t2
col. addr.
RAS
t4 t5 t3 t6
CAS0,CAS1
t9 t10
W
t7 t8
MD0-MD7 Figure 77 Memory Interface - DRAM Write Access Parameter Memory Interface - DRAM Write Access row address setup time row address hold time column address setup time RAS precharge time RAS to CAS delay CAS pulse width Data output setup time Data output hold time RAS to W delay W to CAS setup Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit values Min 50 50 50 110 110 110 100 50 50 50 2000 2000 Max ns ns ns ns ns ns ns ns ns ns Unit
Semiconductor Group
238
10.97
PSB 4860
Electrical Characteristics
t1
t2
RAS
t3 t4
CAS0,CAS1 Figure 78 Memory Interface - DRAM Refresh Cycle Parameter Memory Interface - DRAM Refresh Cycle RAS precharge time RAS low time CAS setup CAS hold Symbol t1 t2 t3 t4 Limit values Min 100 200 100 100 5000 Max ns ns ns ns Unit
Note: The frequency of the DRAM refresh cycle depends on the selected mode. In active mode or normal refresh mode (during power down) the minimal frequency is 64 kHz. In battery backup mode, the refresh frequency is 8 kHz.
Semiconductor Group
239
10.97
PSB 4860
Electrical Characteristics
MA0-MA15
t1
linear address
t2
VPRD
t3 t4
MD0-MD7
Figure 79 Memory Interface - EPROM Read Parameter Memory Interface - EPROM Read Address setup before VPRD VPRD low time Data setup time Data hold time Symbol t1 t2 t3 t4 Limit values Min 110 500 40 0 Max ns ns ns ns Unit
Semiconductor Group
240
10.97
PSB 4860
Electrical Characteristics
MA0-MA11
t1
A16-A23 and FCS0-FCS3
FCS(FCS0-FCS3)
t2
FCLE
t3 t4 t5
FWR
t6 t7
MD0-MD7 Figure 80 Memory Interface - Samsung Command Write Parameter Memory Interface - Samsung Command Write Address setup before FCS, FCLE FCS low time, FCLE high time FWR hold after FCLE rising FWR low time FWR setup before FCLE falling Data setup time Data hold time Symbol Limit values Min t1 t2 t3 t4 t5 t6 t7 100 400 100 200 100 200 50 Max ns ns ns ns ns ns ns Unit
Note: FCS stays low if other cycles follow for the same access.
Semiconductor Group
241
10.97
PSB 4860
Electrical Characteristics
t1
ALE
t2 t3 t4
FWR
t5 t6
MD0-MD7
Figure 81 Memory Interface - Samsung Address Write Parameter Memory Interface - Samsung Address Write ALE high time FWR hold after ALE rising FWR low time FWR setup before ALE falling Data setup time Data hold time Symbol Limit values Min t1 t2 t3 t4 t5 t6 400 100 200 100 200 50 Max ns ns ns ns ns ns Unit
Semiconductor Group
242
10.97
PSB 4860
Electrical Characteristics
t1
FWR
t2 t3
MD0-MD7 Figure 82 Memory Interface - Samsung Data Write Parameter Memory Interface - Samsung Data Write FWR low time Data setup time Data hold time Symbol t1 t2 t3 Limit values Min 200 200 50 Max ns ns ns Unit
Semiconductor Group
243
10.97
PSB 4860
Electrical Characteristics
t1
FOE
t2 t3
MD0-MD7 Figure 83 Memory Interface - Samsung Data Read Parameter Memory Interface - Samsung Data Read FOE low time Data setup time Data hold time Symbol t1 t2 t3 Limit values Min 200 40 0 Max ns ns ns Unit
Semiconductor Group
244
10.97
PSB 4860
Electrical Characteristics
t1
t2
MA13 MA12
t3 t4
MA0-MA11
Figure 84 Auxiliary Parallel Port - Multiplex Mode Parameter Auxiliary Port Interface - Multiplex Mode Active time (MA0-MA15) Gap time (MA0-MA15) Data setup time Data hold time Symbol t1 t2 t3 t4 50 0 Limit values Min Typ 2 125 Max ms s ns ns Unit
Semiconductor Group
245
10.97
PSB 4860
Electrical Characteristics
t1 VDD/VDDP t3 t2
RST
t4
Figure 85 Reset Timing Parameter Reset Timing Symbol t1 t2 t3 t4 0 0.1 1000 Limit values Min Max 20 ms ns ms ns Unit
VDD/VDDP/VDDA rise time 5%-95%
Supply voltages stable to RST high Supply voltages stable to RST low RST high time
Semiconductor Group
246
10.97
PSB 4860
Package Outlines 5 Package Outlines Plastic Package, P-MQFP-80 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 247
Dimensions in mm 10.97
PSB 4860
Index A Abort Clearing Event 82, 119 Functional Description 81 Status Bit 109 Alert Tone Detector Electrical Characteristics 229 Functional Description 46 Registers 146-147 Status Bit 110 Analog Front End Interface Electrical Characteristics 236 Functional Description 55 Registers 122-128 Timing 92 ARAM see Memory Interface Automatic Gain Control Functional Description 59 Registers 169-175 Auxiliary Parallel Port Electrical Characteristics 245 Mode Bits 112 Multiplex Mode 107 Registers 184-189 Static Mode 107 C Caller ID Decoder Electrical Characteristics 228 Functional Description 49 Registers 148-149 Status Bits 109 CNG Detector Electrical Characteristics 229 Functional Description 45 Registers 142-145
Semiconductor Group
Status Bit 110 CPT Detector Electrical Characteristics 228 Functional Description 47 Registers 150-154 Status Bit 110 D Digital Interface Functional Description 56 Mode Bits 112 Registers 129-135 DRAM see Memory Interface DTMF Detector Electrical Characteristics 228 Functional Description 44 Registers 159-161 Status Bit 110 DTMF Generator Functional Description 51 Registers 137-141 E EPROM see Memory Interface Equalizer Functional Description 61 Registers 162-164 Execution Times File Commands 77 F File Commands Access File Descriptor 72 Compress 71 Create Next New 69 Delete 71
248 10.97
PSB 4860
Index Execution Times 77 New File 69 Open 69 Read Binary Data 73 Registers 176-180 Restrictions 78 Seek 70 Status Bits 110 Tailcut 71 Write Binary Data 74 Type Audio 64 Binary 64 Phrase 65 User Data Word 66 Flash Memory see Memory Interface G Group Listening 38 H Hardware Configuration Functional Description 82 Registers 111 I Interrupt Functional Description 80 Pin Configuration 111 Register 121 IOM(R)-2 Interface Electrical Characteristics 232-233 Functional Description 86 see also: Digital Interface L Line Echo Canceller Functional Description 42 Registers 155-158 Loudhearing 38 M Memory Interface ARAM/DRAM Connection Diagram 99 Electrical Characteristics 237-239 Refresh 101, 113 Timing 100 EPROM Connection Diagram 102 Electrical Characteristics 240 Timing 102 Flash Connection Diagram 103 Electrical Characteristics 241-244 In-Circuit Programming 98, 113 Multiple Devices 104 Timing 105 Register 120 Supported Devices 98 Memory Management Activation 68 Directories 63 ExecutionTimes 77 Files 64 Garbage Collection 72 Initialization 67 Memory Status 72 Overview 63 Status 65 O Oscillator Electrical Characteristics 231 Mode Bits 112 P Power Down Functional Description 79
249 10.97
Semiconductor Group
PSB 4860
Index Status Bit 111 R Real Time Clock Configuration Bits 111 Functional Description 79 Oscillator 231 Registers 182-183 Recompression 71 Reset Electrical Characteristics 246 Functional Description 79 Register Values 115 Restrictions File Commands 78 Modules 83 Revision Functional Description 82 Register 119 S Serial Control Interface Command Opcodes 97 Electrical Characteristics 235 Functional Description 94 Signals Encoding 117 Reference Table 117 Speakerphone Functional Description Automatic Gain Control 38 Control 37 Echo Cancellation 28 Echo Suppression 30 Overview 27 Speech Comparator 35 Speech Detector 32 Registers 190-223 Speech Coder Functional Description 52 Registers 165-167 Speech Decoder Functional Description 54 Register 168 SPS Outputs Functional Description 38, 79 Register 181 SSDI Interface Electrical Characteristics 232-234 Functional Description 90 see also: Digital Interface Status Register Definition 109 Update Timing 230 U Universal Attenuator Functional Description 58 Register 136
Semiconductor Group
250
10.97

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